5  * SPDX-License-Identifier:     GPL-2.0+
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/ap.h>
20 /* Tegra124-specific CPU init code */
28 	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */  in enable_cpu_power_rail()
35 	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),  in enable_cpu_power_rail()
38 	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);  in enable_cpu_power_rail()
41 	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);  in enable_cpu_power_rail()
42 	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);  in enable_cpu_power_rail()
53 	/* Wait for PLL-X to lock */  in enable_cpu_clocks()
55 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in enable_cpu_clocks()
57 	} while ((reg & (1 << pllinfo->lock_det)) == 0);  in enable_cpu_clocks()
64 	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);  in enable_cpu_clocks()
65 	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);  in enable_cpu_clocks()
71 	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);  in enable_cpu_clocks()
91 	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
92 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
94 	/* Clear the SW-controlled reset of the slow cluster */  in remove_cpu_resets()
97 	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
99 	/* Clear the SW-controlled reset of the fast cluster */  in remove_cpu_resets()
105 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
123 	clrbits_le32(&flow->cluster_control, 1);  in tegra124_init_clocks()
125 	/* Change the oscillator drive strength */  in tegra124_init_clocks()
126 	val = readl(&clkrst->crc_osc_ctrl);  in tegra124_init_clocks()
129 	writel(val, &clkrst->crc_osc_ctrl);  in tegra124_init_clocks()
132 	val = readl(&pmc->pmc_osc_edpd_over);  in tegra124_init_clocks()
135 	writel(val, &pmc->pmc_osc_edpd_over);  in tegra124_init_clocks()
138 	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);  in tegra124_init_clocks()
144 	writel(val, &clkrst->crc_clk_sys_rate);  in tegra124_init_clocks()
146 	/* Enable clocks to required peripherals. TBD - minimize this list */  in tegra124_init_clocks()
201 	reg = readl(&pmc->pmc_pwrgate_status);  in is_partition_powered()
212 		/* No, toggle the partition power state (OFF -> ON) */  in power_partition()
214 		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);  in power_partition()
234 	/* Power up the fast cluster non-CPU partition */  in powerup_cpus()
253 	/* Set power-gating timer multiplier */  in start_cpu()
255 	       &pmc->pmc_pwrgate_timer_mult);  in start_cpu()