465 	struct clk_rst_ctlr *clkrst =  in clock_get_osc_freq()  local
469 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
481 	struct clk_rst_ctlr *clkrst =  in get_periph_source_reg()  local
487 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
494 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
496 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
577 	struct clk_rst_ctlr *clkrst =  in clock_set_enable()  local
585 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
587 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
598 	struct clk_rst_ctlr *clkrst =  in reset_set_enable()  local
606 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
608 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
657 	struct clk_rst_ctlr *clkrst =  in clock_early_init()  local
666 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);  in clock_early_init()
699 	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);  in clock_early_init()
703 	setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));  in clock_early_init()
710 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()