2  * (C) Copyright 2010-2015
5  * SPDX-License-Identifier:     GPL-2.0+
13 #include <asm/arch/sysctr.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
48 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
142 	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),	/* MIPI base-band HSI */
221  *	SPDIF - which is both 0x08 and 0x0c
224 #define NONE(name) (-1)
469 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
487 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
491 	assert(internal_id != -1);  in get_periph_source_reg()
493 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
494 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
496 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
505 		return -1;  in get_periph_clock_info()
509 		return -1;  in get_periph_clock_info()
513 		return -1;  in get_periph_clock_info()
554  * @return mux value (0-4, or -1 if not found)
572 	return -1;  in get_periph_clock_source()
585 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
587 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
606 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
608 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
666 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);  in clock_early_init()
699 	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);  in clock_early_init()
703 	setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));  in clock_early_init()
708 	data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);  in clock_early_init()
709 	data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);  in clock_early_init()
710 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
716 	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;  in arch_timer_init()  local
727 	writel(freq, &sysctr->cntfid0);  in arch_timer_init()
729 	val = readl(&sysctr->cntcr);  in arch_timer_init()
731 	writel(val, &sysctr->cntcr);  in arch_timer_init()
755 	{ -1, },