172 	ACCESS_ONCE(ivc->tx_channel->w_count) =  in tegra_ivc_advance_tx()
173 			ACCESS_ONCE(ivc->tx_channel->w_count) + 1;  in tegra_ivc_advance_tx()
193 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_check_read()
214 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_check_write()
217 	if (!tegra_ivc_channel_full(ivc, ivc->tx_channel))  in tegra_ivc_check_write()
221 	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_check_write()
222 	return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0;  in tegra_ivc_check_write()
294 	*frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos);  in tegra_ivc_write_get_next_frame()
308 	tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos);  in tegra_ivc_write_advance()
317 	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_write_advance()
325 	tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_write_advance()
327 	if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1)  in tegra_ivc_write_advance()
374 		ivc->tx_channel->w_count = 0;  in tegra_ivc_channel_notified()
390 		ivc->tx_channel->state = ivc_state_ack;  in tegra_ivc_channel_notified()
392 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
398 	} else if (ivc->tx_channel->state == ivc_state_sync &&  in tegra_ivc_channel_notified()
411 		ivc->tx_channel->w_count = 0;  in tegra_ivc_channel_notified()
428 		ivc->tx_channel->state = ivc_state_established;  in tegra_ivc_channel_notified()
430 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
436 	} else if (ivc->tx_channel->state == ivc_state_ack) {  in tegra_ivc_channel_notified()
450 		ivc->tx_channel->state = ivc_state_established;  in tegra_ivc_channel_notified()
452 		tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_notified()
467 	if (ivc->tx_channel->state != ivc_state_established)  in tegra_ivc_channel_notified()
477 	ivc->tx_channel->state = ivc_state_sync;  in tegra_ivc_channel_reset()
479 	tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset);  in tegra_ivc_channel_reset()
545 	ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base;  in tegra_ivc_init()