arm/mach-tegra/cpu.c

2  * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
4  * SPDX-License-Identifier:	GPL-2.0
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
25 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
42  * Timing tables for each SOC for all four oscillator options.
49 	 * ------------------------------
67 	 * ------------------------------
85 	 * ------------------------------
103 	 * ------------------------------
121 	 * ------------------------------
139 	 * ------------------------------
162 	reg = readl(&clkrst->crc_pllx_misc3);
164 	writel(reg, &clkrst->crc_pllx_misc3);
167 	      readl(&clkrst->crc_pllx_misc3));
180 	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
188 	reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
189 	reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
190 	writel(reg, &pll->pll_base);
194 		reg = (cpcon << pllinfo->kcp_shift);
205 	writel(reg, &pll->pll_misc);
208 	reg = readl(&pll->pll_base);
210 	writel(reg, &pll->pll_base);
213 	/* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
214 	reg = readl(&pll->pll_misc);
215 	if (pllinfo->lock_ena < 32)
216 		reg |= (1 << pllinfo->lock_ena);
217 	writel(reg, &pll->pll_misc);
221 	reg = readl(&pll->pll_base);
223 	writel(reg, &pll->pll_base);
232 	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
256 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
277 		/* Wait until all clocks are stable */
280 		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
281 		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
288 	clk = readl(&clkrst->crc_clk_cpu_cmplx);
296 	writel(clk, &clkrst->crc_clk_cpu_cmplx);
305 	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
315 	reg = readl(&pmc->pmc_remove_clamping);
317 	writel(reg, &pmc->pmc_remove_clamping);
319 	/* Give I/O signals time to stabilize */
331 		/* Toggle the CPU power state (OFF -> ON) */
332 		reg = readl(&pmc->pmc_pwrgate_toggle);
335 		writel(reg, &pmc->pmc_pwrgate_toggle);
339 			if (timeout-- == 0)