Lines Matching +full:8 +full:- +full:cpu
2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
16 #include "cpu.h"
25 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; in get_num_cpus()
49 * ------------------------------
51 * PLLX_BASE n 17: 8 10
53 * PLLX_MISC cpcon 11: 8 4
57 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
67 * ------------------------------
69 * PLLX_BASE n 17: 8 10
71 * PLLX_MISC cpcon 11: 8 4
75 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
85 * ------------------------------
87 * PLLX_BASE n 17: 8 10
89 * PLLX_MISC cpcon 11: 8 4
92 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
93 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
94 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
95 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
103 * ------------------------------
105 * PLLX_BASE n 15: 8 8
106 * PLLX_BASE m 7: 0 8
121 * ------------------------------
123 * PLLX_BASE n 15: 8 8
124 * PLLX_BASE m 7: 0 8
139 * ------------------------------
141 * PLLX_BASE n 15: 8 8
142 * PLLX_BASE m 7: 0 8
162 reg = readl(&clkrst->crc_pllx_misc3); in pllx_set_iddq()
164 writel(reg, &clkrst->crc_pllx_misc3); in pllx_set_iddq()
167 readl(&clkrst->crc_pllx_misc3)); in pllx_set_iddq()
180 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
188 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
189 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
190 writel(reg, &pll->pll_base); in pllx_set_rate()
194 reg = (cpcon << pllinfo->kcp_shift); in pllx_set_rate()
205 writel(reg, &pll->pll_misc); in pllx_set_rate()
208 reg = readl(&pll->pll_base); in pllx_set_rate()
210 writel(reg, &pll->pll_base); in pllx_set_rate()
213 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */ in pllx_set_rate()
214 reg = readl(&pll->pll_misc); in pllx_set_rate()
215 if (pllinfo->lock_ena < 32) in pllx_set_rate()
216 reg |= (1 << pllinfo->lock_ena); in pllx_set_rate()
217 writel(reg, &pll->pll_misc); in pllx_set_rate()
221 reg = readl(&pll->pll_base); in pllx_set_rate()
223 writel(reg, &pll->pll_base); in pllx_set_rate()
232 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; in init_pllx()
256 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); in init_pllx()
267 * Regardless of whether the request is to enable or disable the CPU in enable_cpu_clock()
268 * clock, every processor in the CPU complex except the master (CPU 0) in enable_cpu_clock()
280 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); in enable_cpu_clock()
281 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); in enable_cpu_clock()
285 * Read the register containing the individual CPU clock enables and in enable_cpu_clock()
288 clk = readl(&clkrst->crc_clk_cpu_cmplx); in enable_cpu_clock()
293 /* Stop/Unstop the CPU clock */ in enable_cpu_clock()
296 writel(clk, &clkrst->crc_clk_cpu_cmplx); in enable_cpu_clock()
305 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; in is_cpu_powered()
314 /* Remove the clamps on the CPU I/O signals */ in remove_cpu_io_clamps()
315 reg = readl(&pmc->pmc_remove_clamping); in remove_cpu_io_clamps()
317 writel(reg, &pmc->pmc_remove_clamping); in remove_cpu_io_clamps()
331 /* Toggle the CPU power state (OFF -> ON) */ in powerup_cpu()
332 reg = readl(&pmc->pmc_pwrgate_toggle); in powerup_cpu()
335 writel(reg, &pmc->pmc_pwrgate_toggle); in powerup_cpu()
339 if (timeout-- == 0) in powerup_cpu()
340 printf("CPU failed to power up!\n"); in powerup_cpu()
346 * Remove the I/O clamps from CPU power partition. in powerup_cpu()
347 * Recommended only on a Warm boot, if the CPU partition gets in powerup_cpu()
358 * NOTE: Regardless of whether the request is to hold the CPU in reset in reset_A9_cpu()
359 * or take it out of reset, every processor in the CPU complex in reset_A9_cpu()
360 * except the master (CPU 0) will be held in reset because the in reset_A9_cpu()
362 * are multiple processors in the CPU complex. in reset_A9_cpu()
366 int cpu; in reset_A9_cpu() local
369 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ in reset_A9_cpu()
370 for (cpu = 1; cpu < num_cpus; cpu++) in reset_A9_cpu()
371 reset_cmplx_set_enable(cpu, mask, 1); in reset_A9_cpu()
374 /* Enable/Disable master CPU reset */ in reset_A9_cpu()
396 /* Unlock the CPU CoreSight interfaces */ in clock_enable_coresight()