164 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,  in clock_ll_set_source_divisor()  argument
167 	u32 *reg = get_periph_source_reg(periph_id);  in clock_ll_set_source_divisor()
181 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,  in clock_ll_set_source_bits()  argument
184 	u32 *reg = get_periph_source_reg(periph_id);  in clock_ll_set_source_bits()
209 static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)  in clock_ll_get_source_bits()  argument
211 	u32 *reg = get_periph_source_reg(periph_id);  in clock_ll_get_source_bits()
232 void clock_ll_set_source(enum periph_id periph_id, unsigned source)  in clock_ll_set_source()  argument
234 	clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);  in clock_ll_set_source()
310 unsigned long clock_get_periph_rate(enum periph_id periph_id,  in clock_get_periph_rate()  argument
313 	u32 *reg = get_periph_source_reg(periph_id);  in clock_get_periph_rate()
317 	switch (periph_id) {  in clock_get_periph_rate()
407 static int adjust_periph_pll(enum periph_id periph_id, int source,  in adjust_periph_pll()  argument
410 	u32 *reg = get_periph_source_reg(periph_id);  in adjust_periph_pll()
420 	clock_ll_set_source_bits(periph_id, mux_bits, source);  in adjust_periph_pll()
426 enum clock_id clock_get_periph_parent(enum periph_id periph_id)  in clock_get_periph_parent()  argument
431 	err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);  in clock_get_periph_parent()
435 	source = clock_ll_get_source_bits(periph_id, mux_bits);  in clock_get_periph_parent()
437 	return get_periph_clock_id(periph_id, source);  in clock_get_periph_parent()
440 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,  in clock_adjust_periph_pll_div()  argument
449 	source = get_periph_clock_source(periph_id, parent, &mux_bits,  in clock_adjust_periph_pll_div()
458 	if (adjust_periph_pll(periph_id, source, mux_bits, divider))  in clock_adjust_periph_pll_div()
460 	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,  in clock_adjust_periph_pll_div()
461 		get_periph_source_reg(periph_id),  in clock_adjust_periph_pll_div()
462 		readl(get_periph_source_reg(periph_id)));  in clock_adjust_periph_pll_div()
465 	effective_rate = clock_get_periph_rate(periph_id, parent);  in clock_adjust_periph_pll_div()
474 unsigned clock_start_periph_pll(enum periph_id periph_id,  in clock_start_periph_pll()  argument
479 	reset_set_enable(periph_id, 1);  in clock_start_periph_pll()
480 	clock_enable(periph_id);  in clock_start_periph_pll()
482 	effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,  in clock_start_periph_pll()
485 	reset_set_enable(periph_id, 0);  in clock_start_periph_pll()
489 void clock_enable(enum periph_id clkid)  in clock_enable()
494 void clock_disable(enum periph_id clkid)  in clock_disable()
499 void reset_periph(enum periph_id periph_id, int us_delay)  in reset_periph()  argument
502 	reset_set_enable(periph_id, 1);  in reset_periph()
506 	reset_set_enable(periph_id, 0);  in reset_periph()
643 void clock_ll_start_uart(enum periph_id periph_id)  in clock_ll_start_uart()  argument
646 	reset_set_enable(periph_id, 1);  in clock_ll_start_uart()
647 	clock_enable(periph_id);  in clock_ll_start_uart()
648 	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */  in clock_ll_start_uart()
654 	reset_set_enable(periph_id, 0);  in clock_ll_start_uart()
660 	enum periph_id id;  in clock_decode_periph_id()
709 	for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {  in clock_init()
710 		enum periph_id periph_id;  in clock_init()  local
714 		periph_id = periph_clk_init_table[i].periph_id;  in clock_init()
717 		source = get_periph_clock_source(periph_id, parent, &mux_bits,  in clock_init()
719 		clock_ll_set_source_bits(periph_id, mux_bits, source);  in clock_init()