63 	struct clk_rst_ctlr *clkrst =  in clock_get_osc_bypass()  local
67 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_bypass()
74 	struct clk_rst_ctlr *clkrst =  in get_pll()  local
82 	return &clkrst->crc_pll[clkid];  in get_pll()
513 	struct clk_rst_ctlr *clkrst =  in reset_cmplx_set_enable()  local
523 		writel(mask, &clkrst->crc_cpu_cmplx_set);  in reset_cmplx_set_enable()
525 		writel(mask, &clkrst->crc_cpu_cmplx_clr);  in reset_cmplx_set_enable()
725 	struct clk_rst_ctlr *clkrst =  in set_avp_clock_source()  local
734 	writel(val, &clkrst->crc_sclk_brst_pol);  in set_avp_clock_source()
745 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;  in tegra30_set_up_pllp()  local
794 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra30_set_up_pllp()
800 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra30_set_up_pllp()
805 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra30_set_up_pllp()
811 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra30_set_up_pllp()