72 static struct clk_pll *get_pll(enum clock_id clkid)  in get_pll()  argument
77 	assert(clock_id_is_pll(clkid));  in get_pll()
78 	if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {  in get_pll()
79 		debug("%s: Invalid PLL %d\n", __func__, clkid);  in get_pll()
82 	return &clkrst->crc_pll[clkid];  in get_pll()
85 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)  in clock_get_simple_pll()  argument
90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,  in clock_ll_read_pll()  argument
93 	struct clk_pll *pll = get_pll(clkid);  in clock_ll_read_pll()
94 	struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];  in clock_ll_read_pll()
97 	assert(clkid != CLOCK_ID_USB);  in clock_ll_read_pll()
100 	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)  in clock_ll_read_pll()
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,  in clock_start_pll()  argument
118 	struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];  in clock_start_pll()
122 	if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {  in clock_start_pll()
123 		pll = get_pll(clkid);  in clock_start_pll()
125 		simple_pll = clock_get_simple_pll(clkid);  in clock_start_pll()
127 			debug("%s: Uknown simple PLL %d\n", __func__, clkid);  in clock_start_pll()
264 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)  in clock_set_pllout()  argument
266 	struct clk_pll *pll = get_pll(clkid);  in clock_set_pllout()
269 	if (!clock_id_is_pll(clkid))  in clock_set_pllout()
272 	if (pllout + 1 > pll_num_clkouts[clkid])  in clock_set_pllout()
275 	div = clk_get_divider(8, pll_rate[clkid], rate);  in clock_set_pllout()
489 void clock_enable(enum periph_id clkid)  in clock_enable()  argument
491 	clock_set_enable(clkid, 1);  in clock_enable()
494 void clock_disable(enum periph_id clkid)  in clock_disable()  argument
496 	clock_set_enable(clkid, 0);  in clock_disable()
533 unsigned clock_get_rate(enum clock_id clkid)  in clock_get_rate()  argument
538 	struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];  in clock_get_rate()
541 	if (clkid == CLOCK_ID_OSC)  in clock_get_rate()
544 	if (clkid == CLOCK_ID_CLK_M)  in clock_get_rate()
547 	pll = get_pll(clkid);  in clock_get_rate()
565 	if (clkid != CLOCK_ID_PERIPH)  in clock_get_rate()
589 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)  in clock_set_rate()  argument
593 	struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];  in clock_set_rate()
595 	pll = get_pll(clkid);  in clock_set_rate()
609 	if (clkid == CLOCK_ID_PERIPH) {  in clock_set_rate()