Lines Matching +full:oscillator +full:- +full:stable +full:- +full:time
2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/arch-tegra/ap.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/timer.h>
29 * The oscillator frequency is fixed to one of four set values. Based on this
67 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_bypass()
82 return &clkrst->crc_pll[clkid]; in get_pll()
101 return -1; in clock_ll_read_pll()
102 data = readl(&pll->pll_base); in clock_ll_read_pll()
103 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
105 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()
106 data = readl(&pll->pll_misc); in clock_ll_read_pll()
108 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; in clock_ll_read_pll()
109 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; in clock_ll_read_pll()
134 * values for all of the PLLs used in U-Boot, with any in clock_start_pll()
140 misc_data = readl(&pll->pll_misc); in clock_start_pll()
142 misc_data = readl(&simple_pll->pll_misc); in clock_start_pll()
143 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); in clock_start_pll()
144 misc_data |= cpcon << pllinfo->kcp_shift; in clock_start_pll()
145 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); in clock_start_pll()
146 misc_data |= lfcon << pllinfo->kvco_shift; in clock_start_pll()
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
149 data |= divp << pllinfo->p_shift; in clock_start_pll()
153 writel(misc_data, &pll->pll_misc); in clock_start_pll()
154 writel(data, &pll->pll_base); in clock_start_pll()
156 writel(misc_data, &simple_pll->pll_misc); in clock_start_pll()
157 writel(data, &simple_pll->pll_base); in clock_start_pll()
160 /* calculate the stable time */ in clock_start_pll()
203 return -1; in clock_ll_set_source_bits()
228 return -1; in clock_ll_get_source_bits()
252 divider += rate - 1; in clk_get_divider()
255 if ((s64)divider - 2 < 0) in clk_get_divider()
258 if ((s64)divider - 2 >= max_divider) in clk_get_divider()
259 return -1; in clk_get_divider()
261 return divider - 2; in clk_get_divider()
270 return -1; in clock_set_pllout()
273 return -1; in clock_set_pllout()
278 return -1; in clock_set_pllout()
286 clrsetbits_le32(&pll->pll_out[pllout >> 1], in clock_set_pllout()
331 * get_rate_from_divider() would probably require remove the -2 in clock_get_periph_rate()
346 div -= 2; in clock_get_periph_rate()
358 * required child clock rate. This function assumes that a second-stage
364 * @param extra_div value for the second-stage divisor (not set if this
365 * function returns -1.
366 * @return divider which should be used, or -1 if nothing is valid
373 int best_divider = -1; in find_best_divider()
383 int error = rate - effective_rate; in find_best_divider()
386 if (divider != -1 && error < best_error) { in find_best_divider()
393 /* return what we found - *extra_div will already be set */ in find_best_divider()
401 * @param source Source number (0-3 or 0-7)
404 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
418 return -1; in adjust_periph_pll()
459 return -1U; in clock_adjust_periph_pll_div()
523 writel(mask, &clkrst->crc_cpu_cmplx_set); in reset_cmplx_set_enable()
525 writel(mask, &clkrst->crc_cpu_cmplx_clr); in reset_cmplx_set_enable()
550 base = readl(&pll->pll_base); in clock_get_rate()
552 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); in clock_get_rate()
553 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
563 * U-Boot at the time of writing this comment. in clock_get_rate()
567 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; in clock_get_rate()
586 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
597 base_reg = readl(&pll->pll_base); in clock_set_rate()
600 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
601 base_reg |= m << pllinfo->m_shift; in clock_set_rate()
603 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()
604 base_reg |= n << pllinfo->n_shift; in clock_set_rate()
606 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); in clock_set_rate()
607 base_reg |= p << pllinfo->p_shift; in clock_set_rate()
616 if (base_reg != readl(&pll->pll_base)) in clock_set_rate()
618 return pllp_valid ? 1 : -1; in clock_set_rate()
624 writel(base_reg, &pll->pll_base); in clock_set_rate()
627 misc_reg = readl(&pll->pll_misc); in clock_set_rate()
628 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); in clock_set_rate()
629 misc_reg |= cpcon << pllinfo->kcp_shift; in clock_set_rate()
630 writel(misc_reg, &pll->pll_misc); in clock_set_rate()
634 writel(base_reg, &pll->pll_base); in clock_set_rate()
638 writel(base_reg, &pll->pll_base); in clock_set_rate()
653 /* De-assert reset to UART */ in clock_ll_start_uart()
666 return -1; in clock_decode_periph_id()
676 u32 reg = readl(&pll->pll_base); in clock_verify()
680 return -1; in clock_verify()
709 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) { in clock_init()
734 writel(val, &clkrst->crc_sclk_brst_pol); in set_avp_clock_source()
741 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
784 * oscillator being wrong. in tegra30_set_up_pllp()
794 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
800 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra30_set_up_pllp()
805 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
811 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra30_set_up_pllp()
821 setbits_le32(&pmc->pmc_clk_out_cntrl, in clock_external_output()
822 1 << (2 + (clk_id - 1) * 8)); in clock_external_output()
825 return -EINVAL; in clock_external_output()