Lines Matching refs:mctl_phy
361 struct sunxi_mctl_phy_reg *mctl_phy; in mctl_channel_init() local
456 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
459 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE; in mctl_channel_init()
629 &mctl_phy->dcr); in mctl_channel_init()
633 clrbits_le32(&mctl_phy->dsgcr, (3 << 6)); in mctl_channel_init()
635 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
636 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
637 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
638 writel(mr[3], &mctl_phy->mr3); in mctl_channel_init()
646 &mctl_phy->dtpr[0]); in mctl_channel_init()
649 &mctl_phy->dtpr[1]); in mctl_channel_init()
654 &mctl_phy->dtpr[2]); in mctl_channel_init()
664 writel(0x42C21590, &mctl_phy->ptr[0]); in mctl_channel_init()
665 writel(0xD05612C0, &mctl_phy->ptr[1]); in mctl_channel_init()
673 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
674 writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]); in mctl_channel_init()
683 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
684 writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]); in mctl_channel_init()
688 writel(0x00203131, &mctl_phy->acmdlr); in mctl_channel_init()
692 &mctl_phy->dtcr); in mctl_channel_init()
695 debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0])); in mctl_channel_init()
696 writel(0x7C000285, &mctl_phy->dx[2].gcr[0]); in mctl_channel_init()
697 writel(0x7C000285, &mctl_phy->dx[3].gcr[0]); in mctl_channel_init()
699 clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff, in mctl_channel_init()
701 clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff, in mctl_channel_init()
703 clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff, in mctl_channel_init()
710 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
711 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
718 clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff, in mctl_channel_init()
721 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
724 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
729 writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */ in mctl_channel_init()
730 writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */ in mctl_channel_init()
731 writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */ in mctl_channel_init()
736 setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */ in mctl_channel_init()
738 clrsetbits_le32(&mctl_phy->pgcr[1], in mctl_channel_init()
742 setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */ in mctl_channel_init()
744 setbits_le32(&mctl_phy->pllcr, in mctl_channel_init()
749 clrbits_le32(&mctl_phy->pgcr[0], 0x3f); in mctl_channel_init()
753 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3); in mctl_channel_init()
755 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573); in mctl_channel_init()
760 while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) { in mctl_channel_init()
795 if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) { in mctl_channel_init()
813 clrbits_le32(&mctl_phy->pgcr[3], (1 << 25)); in mctl_channel_init()