Lines Matching refs:mctl_ctl
188 struct sunxi_mctl_ctl_reg *mctl_ctl = in mctl_ctl_sched_init() local
192 writel(SCHED_CONFIG, &mctl_ctl->sched); in mctl_ctl_sched_init()
193 writel(PERFHPR0_CONFIG, &mctl_ctl->perfhpr0); in mctl_ctl_sched_init()
194 writel(PERFHPR1_CONFIG, &mctl_ctl->perfhpr1); in mctl_ctl_sched_init()
195 writel(PERFLPR0_CONFIG, &mctl_ctl->perflpr0); in mctl_ctl_sched_init()
196 writel(PERFLPR1_CONFIG, &mctl_ctl->perflpr1); in mctl_ctl_sched_init()
197 writel(PERFWR0_CONFIG, &mctl_ctl->perfwr0); in mctl_ctl_sched_init()
198 writel(PERFWR1_CONFIG, &mctl_ctl->perfwr1); in mctl_ctl_sched_init()
360 struct sunxi_mctl_ctl_reg *mctl_ctl; in mctl_channel_init() local
455 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
458 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; in mctl_channel_init()
482 &mctl_ctl->init[0]); in mctl_channel_init()
484 &mctl_ctl->init[1]); in mctl_channel_init()
487 &mctl_ctl->init[3]); in mctl_channel_init()
489 &mctl_ctl->init[4]); in mctl_channel_init()
491 &mctl_ctl->init[5]); in mctl_channel_init()
500 &mctl_ctl->init[0]); in mctl_channel_init()
502 &mctl_ctl->init[1]); in mctl_channel_init()
506 &mctl_ctl->init[2]); in mctl_channel_init()
508 &mctl_ctl->init[3]); in mctl_channel_init()
510 &mctl_ctl->init[4]); in mctl_channel_init()
515 &mctl_ctl->init[5]); in mctl_channel_init()
538 &mctl_ctl->dramtmg[0]); in mctl_channel_init()
541 &mctl_ctl->dramtmg[1]); in mctl_channel_init()
544 &mctl_ctl->dramtmg[2]); in mctl_channel_init()
550 &mctl_ctl->dramtmg[3]); in mctl_channel_init()
553 &mctl_ctl->dramtmg[4]); in mctl_channel_init()
556 &mctl_ctl->dramtmg[5]); in mctl_channel_init()
570 writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]); in mctl_channel_init()
573 &mctl_ctl->rfshtmg); in mctl_channel_init()
578 &mctl_ctl->dfitmg[0]); in mctl_channel_init()
589 clrbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN); in mctl_channel_init()
591 setbits_le32(&mctl_ctl->dfiupd[0], MCTL_DFIUPD0_DIS_AUTO_CTRLUPD); in mctl_channel_init()
599 &mctl_ctl->mstr); in mctl_channel_init()
603 (MCTL_DIV2(tZQCS)), &mctl_ctl->zqctrl[0]); in mctl_channel_init()
610 &mctl_ctl->zqctrl[1]); in mctl_channel_init()
613 &mctl_ctl->zqctrl[0]); in mctl_channel_init()
616 &mctl_ctl->zqctrl[1]); in mctl_channel_init()
620 setbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN); in mctl_channel_init()
622 setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
734 setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
804 while ((readl(&mctl_ctl->stat) & 0x1) != 0x1) { in mctl_channel_init()
816 debug("DFIMISC before writing 0: 0x%x\n", readl(&mctl_ctl->dfimisc)); in mctl_channel_init()
817 writel(0, &mctl_ctl->dfimisc); in mctl_channel_init()
820 clrbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()