Lines Matching +full:ps +full:- +full:speed
4 * (C) Copyright 2007-2015
9 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
11 * SPDX-License-Identifier: GPL-2.0+
29 * Allwinner as part of the open-source bootloader release (refer to
30 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
39 * Note that the Zynq-documentation provides a very close match for the DDR
45 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
51 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
53 * 2) Only 2T-mode has been implemented and tested.
65 * The driver should be driven from a device-tree based configuration that
67 * frequency and speed-bin information)---the data structures used in the
71 * To enable a device-tree based configuration of the sun9i platform, we
73 * into SRAM A1 (40KB) and next into SRAM A2 (160KB)---which would be the
74 * stage to initialise the platform via the device-tree---before having
75 * the full U-Boot run from DDR.
82 * sub-ns timings, such as 7.5ns without losing precision or resorting to
87 u32 ps; member
94 u32 tCKmin; /* in ps */
95 u32 tCKmax; /* in ps */
107 /* Timing information for each speed-bin */
113 * JEDEC Standard No. 79-3F
120 u32 tRAS; /* in ps */
129 u32 tRCD; /* in ps */
130 u32 tRP; /* in ps */
131 u32 tRC; /* in ps */
134 u32 tFAW; /* in ps */
144 /* self-refresh timings */
151 /* power-down timings */
192 writel(SCHED_CONFIG, &mctl_ctl->sched); in mctl_ctl_sched_init()
193 writel(PERFHPR0_CONFIG, &mctl_ctl->perfhpr0); in mctl_ctl_sched_init()
194 writel(PERFHPR1_CONFIG, &mctl_ctl->perfhpr1); in mctl_ctl_sched_init()
195 writel(PERFLPR0_CONFIG, &mctl_ctl->perflpr0); in mctl_ctl_sched_init()
196 writel(PERFLPR1_CONFIG, &mctl_ctl->perflpr1); in mctl_ctl_sched_init()
197 writel(PERFWR0_CONFIG, &mctl_ctl->perfwr0); in mctl_ctl_sched_init()
198 writel(PERFWR1_CONFIG, &mctl_ctl->perfwr1); in mctl_ctl_sched_init()
216 if ((para->dram_clk <= 400)|((para->dram_tpr8 & 0x1)==0)) { in mctl_sys_init()
219 ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) * 2), 0); in mctl_sys_init()
222 ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) / 2), 1); in mctl_sys_init()
225 if (para->dram_tpr13 & (0xf<<18)) { in mctl_sys_init()
237 if(para->dram_tpr13 & (0x1<<18)) in mctl_sys_init()
243 else if(para->dram_tpr13 & (0x1<<19)) in mctl_sys_init()
249 else if(para->dram_tpr13 & (0x1<<20)) in mctl_sys_init()
255 else if(para->dram_tpr13 & (0x1<<21)) in mctl_sys_init()
276 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
278 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
283 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
285 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
295 writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg); in mctl_sys_init()
299 } while (readl(&ccm->dram_clk_cfg) & (1 << 16)); in mctl_sys_init()
300 setbits_le32(&ccm->dram_clk_cfg, (1 << 31)); in mctl_sys_init()
303 setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30)); in mctl_sys_init()
304 writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */ in mctl_sys_init()
310 if ((para->dram_clk <= 400) | ((para->dram_tpr8 & 0x1) == 0)) { in mctl_sys_init()
333 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
336 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in mctl_sys_init()
337 /* TODO if (para->chan == 2) */ in mctl_sys_init()
338 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
346 /* TODO: hard-wired for DDR3 now */ in mctl_com_init()
347 writel(((para->chan == 2) ? MCTL_CR_CHANNEL_DUAL : in mctl_com_init()
350 | MCTL_CR_ROW(para->rows) in mctl_com_init()
351 | ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) in mctl_com_init()
352 | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank), in mctl_com_init()
353 &mctl_com->cr); in mctl_com_init()
355 debug("CR: %d\n", readl(&mctl_com->cr)); in mctl_com_init()
375 * by the definition of each speed bin. in mctl_channel_init()
377 /* const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); */ in mctl_channel_init()
378 const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); in mctl_channel_init()
379 const u32 tRFC = NS2CYCLES_ROUNDUP(para->tRFC); in mctl_channel_init()
380 const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD); in mctl_channel_init()
381 const u32 tRP = PS2CYCLES_ROUNDUP(para->tRP); in mctl_channel_init()
382 const u32 tRC = PS2CYCLES_ROUNDUP(para->tRC); in mctl_channel_init()
383 const u32 tRAS = PS2CYCLES_ROUNDUP(para->tRAS); in mctl_channel_init()
386 const u32 tDLLK = para->tDLLK; in mctl_channel_init()
387 const u32 tRTP = MAX(para->tRTP.ck, PS2CYCLES_ROUNDUP(para->tRTP.ps)); in mctl_channel_init()
388 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps)); in mctl_channel_init()
389 const u32 tWR = NS2CYCLES_FLOOR(para->tWR); in mctl_channel_init()
390 const u32 tMRD = para->tMRD; in mctl_channel_init()
391 const u32 tMOD = MAX(para->tMOD.ck, PS2CYCLES_ROUNDUP(para->tMOD.ps)); in mctl_channel_init()
392 const u32 tCCD = para->tCCD; in mctl_channel_init()
393 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps)); in mctl_channel_init()
394 const u32 tFAW = PS2CYCLES_ROUNDUP(para->tFAW); in mctl_channel_init()
397 /* const u32 tZQinit = MAX(para->tZQinit.ck, in mctl_channel_init()
398 PS2CYCLES_ROUNDUP(para->tZQinit.ps)); */ in mctl_channel_init()
399 const u32 tZQoper = MAX(para->tZQoper.ck, in mctl_channel_init()
400 PS2CYCLES_ROUNDUP(para->tZQoper.ps)); in mctl_channel_init()
401 const u32 tZQCS = MAX(para->tZQCS.ck, in mctl_channel_init()
402 PS2CYCLES_ROUNDUP(para->tZQCS.ps)); in mctl_channel_init()
405 /* const u32 tXPR = MAX(para->tXPR.ck, in mctl_channel_init()
406 PS2CYCLES_ROUNDUP(para->tXPR.ps)); */ in mctl_channel_init()
408 /* power-down timings */ in mctl_channel_init()
409 const u32 tXP = MAX(para->tXP.ck, PS2CYCLES_ROUNDUP(para->tXP.ps)); in mctl_channel_init()
410 const u32 tXPDLL = MAX(para->tXPDLL.ck, in mctl_channel_init()
411 PS2CYCLES_ROUNDUP(para->tXPDLL.ps)); in mctl_channel_init()
412 const u32 tCKE = MAX(para->tCKE.ck, PS2CYCLES_ROUNDUP(para->tCKE.ps)); in mctl_channel_init()
415 * self-refresh timings (keep below power-down timings, as tCKESR in mctl_channel_init()
418 const u32 tXS = MAX(para->tXS.ck, PS2CYCLES_ROUNDUP(para->tXS.ps)); in mctl_channel_init()
419 const u32 tXSDLL = para->tXSDLL; in mctl_channel_init()
420 const u32 tCKSRE = MAX(para->tCKSRE.ck, in mctl_channel_init()
421 PS2CYCLES_ROUNDUP(para->tCKSRE.ps)); in mctl_channel_init()
423 const u32 tCKSRX = MAX(para->tCKSRX.ck, in mctl_channel_init()
424 PS2CYCLES_ROUNDUP(para->tCKSRX.ps)); in mctl_channel_init()
427 const u32 tWLMRD = para->tWLMRD; in mctl_channel_init()
428 /* const u32 tWLDQSEN = para->tWLDQSEN; */ in mctl_channel_init()
429 const u32 tWLO = PS2CYCLES_FLOOR(para->tWLO); in mctl_channel_init()
430 /* const u32 tWLOE = PS2CYCLES_FLOOR(para->tWLOE); */ in mctl_channel_init()
435 for (i = 0; i < para->cl_cwl_numentries; ++i) { in mctl_channel_init()
438 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
439 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
440 CL = para->cl_cwl_table[i].CL; in mctl_channel_init()
441 CWL = para->cl_cwl_table[i].CWL; in mctl_channel_init()
462 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
475 * Refer to Micron document "TN-41-07: DDR3 Power-Up, in mctl_channel_init()
482 &mctl_ctl->init[0]); in mctl_channel_init()
484 &mctl_ctl->init[1]); in mctl_channel_init()
487 &mctl_ctl->init[3]); in mctl_channel_init()
489 &mctl_ctl->init[4]); in mctl_channel_init()
491 &mctl_ctl->init[5]); in mctl_channel_init()
500 &mctl_ctl->init[0]); in mctl_channel_init()
502 &mctl_ctl->init[1]); in mctl_channel_init()
506 &mctl_ctl->init[2]); in mctl_channel_init()
508 &mctl_ctl->init[3]); in mctl_channel_init()
510 &mctl_ctl->init[4]); in mctl_channel_init()
515 &mctl_ctl->init[5]); in mctl_channel_init()
518 /* (DDR3) We always use a burst-length of 8. */ in mctl_channel_init()
525 * rd2wr = RL + BL/2 + 2 - WL (for DDR3) in mctl_channel_init()
526 * rd2wr = RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL (for LPDDR2/LPDDR3) in mctl_channel_init()
528 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
538 &mctl_ctl->dramtmg[0]); in mctl_channel_init()
541 &mctl_ctl->dramtmg[1]); in mctl_channel_init()
544 &mctl_ctl->dramtmg[2]); in mctl_channel_init()
550 &mctl_ctl->dramtmg[3]); in mctl_channel_init()
553 &mctl_ctl->dramtmg[4]); in mctl_channel_init()
556 &mctl_ctl->dramtmg[5]); in mctl_channel_init()
560 (MCTL_TCKCSX << 0), &mctl_ctl->dramtmg[6]); */ in mctl_channel_init()
563 readl(&mctl_ctl->dramtmg[7])); */ in mctl_channel_init()
567 readl(&mctl_ctl->dramtmg[8])); */ in mctl_channel_init()
570 writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]); in mctl_channel_init()
573 &mctl_ctl->rfshtmg); in mctl_channel_init()
575 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
576 writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) | in mctl_channel_init()
577 (1 << 8) | ((MCTL_DIV2(CWL) - 2) << 0), in mctl_channel_init()
578 &mctl_ctl->dfitmg[0]); in mctl_channel_init()
589 clrbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN); in mctl_channel_init()
591 setbits_le32(&mctl_ctl->dfiupd[0], MCTL_DFIUPD0_DIS_AUTO_CTRLUPD); in mctl_channel_init()
593 /* A80-Q7: 2T, 1 rank, DDR3, full-32bit-DQ */ in mctl_channel_init()
595 writel(MCTL_MSTR_DEVICETYPE(para->dram_type) | in mctl_channel_init()
596 MCTL_MSTR_BURSTLENGTH(para->dram_type) | in mctl_channel_init()
597 MCTL_MSTR_ACTIVERANKS(para->rank) | in mctl_channel_init()
599 &mctl_ctl->mstr); in mctl_channel_init()
601 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
603 (MCTL_DIV2(tZQCS)), &mctl_ctl->zqctrl[0]); in mctl_channel_init()
610 &mctl_ctl->zqctrl[1]); in mctl_channel_init()
613 &mctl_ctl->zqctrl[0]); in mctl_channel_init()
616 &mctl_ctl->zqctrl[1]); in mctl_channel_init()
620 setbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN); in mctl_channel_init()
621 /* Disable auto-refresh */ in mctl_channel_init()
622 setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
626 /* TODO: make 2T and 8-bank mode configurable */ in mctl_channel_init()
629 &mctl_phy->dcr); in mctl_channel_init()
632 if (para->dram_type != DRAM_TYPE_DDR3) in mctl_channel_init()
633 clrbits_le32(&mctl_phy->dsgcr, (3 << 6)); in mctl_channel_init()
635 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
636 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
637 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
638 writel(mr[3], &mctl_phy->mr3); in mctl_channel_init()
646 &mctl_phy->dtpr[0]); in mctl_channel_init()
647 writel((tMRD << 0) | ((tMOD - 12) << 2) | (tFAW << 5) | in mctl_channel_init()
649 &mctl_phy->dtpr[1]); in mctl_channel_init()
653 (((tCCD - 4) & 0x1) << 31), in mctl_channel_init()
654 &mctl_phy->dtpr[2]); in mctl_channel_init()
657 /* writel((tDQSCK << 0) | (tDQSCKMAX << 3), &mctl_phy->dtpr[3]); */ in mctl_channel_init()
664 writel(0x42C21590, &mctl_phy->ptr[0]); in mctl_channel_init()
665 writel(0xD05612C0, &mctl_phy->ptr[1]); in mctl_channel_init()
666 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
673 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
674 writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]); in mctl_channel_init()
683 writel((tdinit1 << 20) | tdinit0, &mctl_phy->ptr[3]); in mctl_channel_init()
684 writel((tdinit3 << 18) | tdinit2, &mctl_phy->ptr[4]); in mctl_channel_init()
688 writel(0x00203131, &mctl_phy->acmdlr); in mctl_channel_init()
691 writel(MCTL_DTCR_DEFAULT | MCTL_DTCR_RANKEN(para->rank), in mctl_channel_init()
692 &mctl_phy->dtcr); in mctl_channel_init()
695 debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0])); in mctl_channel_init()
696 writel(0x7C000285, &mctl_phy->dx[2].gcr[0]); in mctl_channel_init()
697 writel(0x7C000285, &mctl_phy->dx[3].gcr[0]); in mctl_channel_init()
699 clrsetbits_le32(&mctl_phy->zq[0].pr, 0xff, in mctl_channel_init()
701 clrsetbits_le32(&mctl_phy->zq[1].pr, 0xff, in mctl_channel_init()
703 clrsetbits_le32(&mctl_phy->zq[2].pr, 0xff, in mctl_channel_init()
706 /* TODO: make configurable & implement non-ODT path */ in mctl_channel_init()
710 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
711 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
718 clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff, in mctl_channel_init()
720 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
721 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
724 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
729 writel(0x04058D02, &mctl_phy->zq[0].cr); /* CK/CA */ in mctl_channel_init()
730 writel(0x04058D02, &mctl_phy->zq[1].cr); /* DX0/DX1 */ in mctl_channel_init()
731 writel(0x04058D02, &mctl_phy->zq[2].cr); /* DX2/DX3 */ in mctl_channel_init()
733 /* Disable auto-refresh prior to data training */ in mctl_channel_init()
734 setbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
736 setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */ in mctl_channel_init()
737 /* TODO: IODDRM (IO DDR-MODE) for DDR3L */ in mctl_channel_init()
738 clrsetbits_le32(&mctl_phy->pgcr[1], in mctl_channel_init()
742 setbits_le32(&mctl_phy->pllcr, 0x3 << 19); /* PLL frequency select */ in mctl_channel_init()
743 /* TODO: single-channel PLL mode??? missing */ in mctl_channel_init()
744 setbits_le32(&mctl_phy->pllcr, in mctl_channel_init()
746 /* setbits_le32(&mctl_phy->pir, MCTL_PIR_PLL_BYPASS); included below */ in mctl_channel_init()
749 clrbits_le32(&mctl_phy->pgcr[0], 0x3f); in mctl_channel_init()
752 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
753 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3); in mctl_channel_init()
755 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573); in mctl_channel_init()
760 while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) { in mctl_channel_init()
761 /* not done yet -- keep spinning */ in mctl_channel_init()
767 /* TODO: not used --- there's a "2rank debug" section here */ in mctl_channel_init()
772 if ((para->dram_type) == 6 || (para->dram_type) == 7) { in mctl_channel_init()
780 * Disable ZCAL after initial--for nand dma debug--20140330 by YSZ * in mctl_channel_init()
781 if (para->dram_tpr13 & (0x1<<31)) { in mctl_channel_init()
790 * TODO: more 2-rank support in mctl_channel_init()
795 if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) { in mctl_channel_init()
804 while ((readl(&mctl_ctl->stat) & 0x1) != 0x1) { in mctl_channel_init()
808 /* TODO: implement time-out */ in mctl_channel_init()
813 clrbits_le32(&mctl_phy->pgcr[3], (1 << 25)); in mctl_channel_init()
816 debug("DFIMISC before writing 0: 0x%x\n", readl(&mctl_ctl->dfimisc)); in mctl_channel_init()
817 writel(0, &mctl_ctl->dfimisc); in mctl_channel_init()
819 /* Enable auto-refresh */ in mctl_channel_init()
820 clrbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
835 reg_val = readl(&mctl_com->cr); in DRAMC_get_dram_size()
838 dram_size = (temp - 6); /* (1 << dram_size) * 512Bytes */ in DRAMC_get_dram_size()
852 dram_size = dram_size - 11; /* (1 << dram_size) MBytes */ in DRAMC_get_dram_size()
881 /* CL/CWL table for the speed bin */ in sunxi_dram_init()
897 .tRTP = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
898 .tWTR = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
901 .tMOD = { .ck = 12, .ps = 15000 }, in sunxi_dram_init()
903 .tRRD = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
907 /* .tZQinit = { .ck = 512, .ps = 640000 }, */ in sunxi_dram_init()
908 .tZQoper = { .ck = 256, .ps = 320000 }, in sunxi_dram_init()
909 .tZQCS = { .ck = 64, .ps = 80000 }, in sunxi_dram_init()
912 /* .tXPR = { .ck = 5, .ps = 10000 }, */ in sunxi_dram_init()
914 /* self-refresh timings */ in sunxi_dram_init()
915 .tXS = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
917 .tCKSRE = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
918 .tCKSRX = { .ck = 5, .ps = 10000 }, in sunxi_dram_init()
920 /* power-down timings */ in sunxi_dram_init()
921 .tXP = { .ck = 3, .ps = 6000 }, in sunxi_dram_init()
922 .tXPDLL = { .ck = 10, .ps = 24000 }, in sunxi_dram_init()
923 .tCKE = { .ck = 3, .ps = 5000 }, in sunxi_dram_init()
936 * https://github.com/allwinner-zh/bootloader.git), as there in sunxi_dram_init()
948 /* dual-channel */ in sunxi_dram_init()
951 clrsetbits_le32(&mctl_com->cr, MCTL_CR_CHANNEL_MASK, in sunxi_dram_init()
954 clrbits_le32(&mctl_com->cr, MCTL_CCR_CH1_CLK_EN); in sunxi_dram_init()