Lines Matching refs:mctl_com
105 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local
177 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_channel_init()
265 struct sunxi_mctl_com_reg * const mctl_com = in mctl_com_init() local
275 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); in mctl_com_init()
278 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init()
296 struct sunxi_mctl_com_reg * const mctl_com = in mctl_port_cfg() local
305 writel(0x00400302, &mctl_com->rmcr[0]); in mctl_port_cfg()
306 writel(0x01000307, &mctl_com->rmcr[1]); in mctl_port_cfg()
307 writel(0x00400302, &mctl_com->rmcr[2]); in mctl_port_cfg()
308 writel(0x01000307, &mctl_com->rmcr[3]); in mctl_port_cfg()
309 writel(0x01000307, &mctl_com->rmcr[4]); in mctl_port_cfg()
310 writel(0x01000303, &mctl_com->rmcr[6]); in mctl_port_cfg()
311 writel(0x01000303, &mctl_com->mmcr[0]); in mctl_port_cfg()
312 writel(0x00400310, &mctl_com->mmcr[1]); in mctl_port_cfg()
313 writel(0x01000307, &mctl_com->mmcr[2]); in mctl_port_cfg()
314 writel(0x01000303, &mctl_com->mmcr[3]); in mctl_port_cfg()
315 writel(0x01800303, &mctl_com->mmcr[4]); in mctl_port_cfg()
316 writel(0x01800303, &mctl_com->mmcr[5]); in mctl_port_cfg()
317 writel(0x01800303, &mctl_com->mmcr[6]); in mctl_port_cfg()
318 writel(0x01800303, &mctl_com->mmcr[7]); in mctl_port_cfg()
319 writel(0x01000303, &mctl_com->mmcr[8]); in mctl_port_cfg()
320 writel(0x00000002, &mctl_com->mmcr[15]); in mctl_port_cfg()
321 writel(0x00000310, &mctl_com->mbagcr[0]); in mctl_port_cfg()
322 writel(0x00400310, &mctl_com->mbagcr[1]); in mctl_port_cfg()
323 writel(0x00400310, &mctl_com->mbagcr[2]); in mctl_port_cfg()
324 writel(0x00000307, &mctl_com->mbagcr[3]); in mctl_port_cfg()
325 writel(0x00000317, &mctl_com->mbagcr[4]); in mctl_port_cfg()
326 writel(0x00000307, &mctl_com->mbagcr[5]); in mctl_port_cfg()
331 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local
352 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in sunxi_dram_init()
356 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in sunxi_dram_init()
359 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); in sunxi_dram_init()
372 clrsetbits_le32(&mctl_com->cr, in sunxi_dram_init()
387 clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK, in sunxi_dram_init()
396 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, in sunxi_dram_init()
404 clrsetbits_le32(&mctl_com->cr, in sunxi_dram_init()