2  * sunxi DRAM controller initialization
6  * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
18  * Unfortunately the only documentation we have on the sun7i DRAM
27 #include <asm/arch/dram.h>
55  * This performs the external DRAM reset by driving the RESET pin low and
61 	struct sunxi_dram_reg *dram =  in mctl_ddr3_reset()  local
74 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
76 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
80 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
82 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
88 	 * automatically by the DRAM controller during the DDR3 initialization  in mctl_ddr3_reset()
90 	 * can't provide sufficient delay at DRAM clock frequencies higher than  in mctl_ddr3_reset()
91 	 * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to  in mctl_ddr3_reset()
101 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_drive()  local
104 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),  in mctl_set_drive()
106 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),  in mctl_set_drive()
114 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_itm_disable()  local
116 	clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);  in mctl_itm_disable()
121 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_itm_enable()  local
123 	clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);  in mctl_itm_enable()
136 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_enable_dll0()  local
138 	clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,  in mctl_enable_dll0()
140 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
143 	clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
146 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);  in mctl_enable_dll0()
153 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_get_number_of_lanes()  local
154 	if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==  in mctl_get_number_of_lanes()
166 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_enable_dllx()  local
172 		clrsetbits_le32(&dram->dllcr[i], 0xf << 14,  in mctl_enable_dllx()
174 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,  in mctl_enable_dllx()
181 		clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |  in mctl_enable_dllx()
186 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,  in mctl_enable_dllx()
231 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_configure_hostport()  local
235 		writel(hpcr_value[i], &dram->hpcr[i]);  in mctl_configure_hostport()
246 	/* setup DRAM PLL */  in mctl_setup_dram_clock()
257 		/* dram = 540MHz */  in mctl_setup_dram_clock()
262 		/* dram = 512MHz */  in mctl_setup_dram_clock()
267 		/* dram = 496MHz */  in mctl_setup_dram_clock()
272 		/* dram = 468MHz */  in mctl_setup_dram_clock()
277 		/* dram = 396MHz */  in mctl_setup_dram_clock()
368 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_dqs_gating_delay()  local
371 	u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
373 	u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
381 	writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
382 	writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
387 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_scan_readpipe()  local
391 	clrbits_le32(&dram->csr, DRAM_CSR_FAILED);  in dramc_scan_readpipe()
392 	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
395 	await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
398 	reg_val = readl(&dram->csr);  in dramc_scan_readpipe()
408 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_clock_output_en()  local
411 		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
413 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
432 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_set_autorefresh_cycle()  local
438 	writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);  in dramc_set_autorefresh_cycle()
457  * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
458  * means that DRAM is currently in self-refresh mode and retaining the old
460  * register to 0 and initialize DRAM in the same way as on any normal reboot
470 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_disable_power_save()  local
471 	writel(0x16510000, &dram->ppwrsctl);  in mctl_disable_power_save()
475  * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
476  * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
478  * right at the time when the DRAM initialization is activated in the
483 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_cke_delay()  local
485 	/* The CKE delay is represented in DRAM clock cycles, multiplied by N  in mctl_set_cke_delay()
489 	 * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i  in mctl_set_cke_delay()
490 	 * with 360 MHz DRAM clock speed). */  in mctl_set_cke_delay()
491 	setbits_le32(&dram->idcr, 0x1ffff);  in mctl_set_cke_delay()
495  * This triggers the DRAM initialization. It performs sending the mode registers
496  * to the DRAM among other things. Very likely the ZQCL command is also getting
497  * executed (to do the initial impedance calibration on the DRAM side of the
503 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_ddr3_initialize()  local
504 	setbits_le32(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
505 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
509  * Perform impedance calibration on the DRAM controller side of the wire.
513 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_impedance()  local
522 	await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
536 	writel((1 << 24) | (1 << 1), &dram->zqcr1);  in mctl_set_impedance()
540 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
545 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
550 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
552 		await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
556 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
559 	writel(DRAM_IOCR_ODT_EN, &dram->iocr);  in mctl_set_impedance()
564 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_init_helper()  local
576 	/* setup DRAM relative clock */  in dramc_init_helper()
584 	/* dram clock off */  in dramc_init_helper()
588 	/* select dram controller 1 */  in dramc_init_helper()
589 	writel(DRAM_CSEL_MAGIC, &dram->csel);  in dramc_init_helper()
595 	/* configure external DRAM */  in dramc_init_helper()
619 	writel(reg_val, &dram->dcr);  in dramc_init_helper()
631 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in dramc_init_helper()
639 	writel(para->tpr0, &dram->tpr0);  in dramc_init_helper()
640 	writel(para->tpr1, &dram->tpr1);  in dramc_init_helper()
641 	writel(para->tpr2, &dram->tpr2);  in dramc_init_helper()
649 	writel(reg_val, &dram->mr);  in dramc_init_helper()
651 	writel(para->emr1, &dram->emr);  in dramc_init_helper()
652 	writel(para->emr2, &dram->emr2);  in dramc_init_helper()
653 	writel(para->emr3, &dram->emr3);  in dramc_init_helper()
656 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
661 		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);  in dramc_init_helper()
663 	/* initialize external DRAM */  in dramc_init_helper()
681 		clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
683 		setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
697 	/* If the dram configuration is not provided, use a default */  in dramc_init()
705 	/* try to autodetect the DRAM bus width and density */  in dramc_init()
731 		/* update the density and re-initialize DRAM again */  in dramc_init()