24 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
39 	       C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);  in clock_init_safe()
43 	       &ccm->ahb0_cfg);  in clock_init_safe()
46 	       &ccm->ahb1_cfg);  in clock_init_safe()
49 	       &ccm->ahb2_cfg);  in clock_init_safe()
52 	       &ccm->apb0_cfg);  in clock_init_safe()
56 	       &ccm->gtbus_cfg);  in clock_init_safe()
59 	       &ccm->cci400_cfg);  in clock_init_safe()
62 	setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));  in clock_init_safe()
63 	setbits_le32(&ccm->apb1_gate, (1 << 24));  in clock_init_safe()
72 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
76 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
80 	setbits_le32(&ccm->apb1_reset_cfg,  in clock_init_uart()
88 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
93 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,  in clock_set_pll1()
99 	       &ccm->pll1_c0_cfg);  in clock_set_pll1()
109 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,  in clock_set_pll1()
115 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll2()  local
120 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,  in clock_set_pll2()
125 	       &ccm->pll2_c1_cfg);  in clock_set_pll2()
130 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,  in clock_set_pll2()
136 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll6()  local
142 	       &ccm->pll6_ddr_cfg);  in clock_set_pll6()
143 	do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS));  in clock_set_pll6()
150 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll12()  local
153 	if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)  in clock_set_pll12()
157 	       &ccm->pll12_periph1_cfg);  in clock_set_pll12()
165 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll4()  local
169 	       &ccm->pll4_periph0_cfg);  in clock_set_pll4()
177 	struct sunxi_ccm_reg *const ccm =  in clock_twi_onoff()  local
185 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
187 		setbits_le32(&ccm->apb1_reset_cfg,  in clock_twi_onoff()
190 		clrbits_le32(&ccm->apb1_reset_cfg,  in clock_twi_onoff()
192 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
201 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll4_periph0()  local
203 	uint32_t rval = readl(&ccm->pll4_periph0_cfg);  in clock_get_pll4_periph0()