22 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
40 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);  in clock_init_safe()
45 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
46 	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))  in clock_init_safe()
49 	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);  in clock_init_safe()
51 	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);  in clock_init_safe()
53 		writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);  in clock_init_safe()
56 	setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);  in clock_init_safe()
57 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
58 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
59 	setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);  in clock_init_safe()
67 	struct sunxi_ccm_reg * const ccm =  in clock_init_sec()  local
72 	setbits_le32(&ccm->ccu_sec_switch,  in clock_init_sec()
86 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
93 	       &ccm->apb2_div);  in clock_init_uart()
96 	setbits_le32(&ccm->apb2_gate,  in clock_init_uart()
101 	setbits_le32(&ccm->apb2_reset_cfg,  in clock_init_uart()
113 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
130 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
138 	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);  in clock_set_pll1()
145 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
151 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3()  local
156 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
163 	       &ccm->pll3_cfg);  in clock_set_pll3()
169 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3_factors()  local
175 	       &ccm->pll3_cfg);  in clock_set_pll3_factors()
177 	while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))  in clock_set_pll3_factors()
184 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll5()  local
190 	clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |  in clock_set_pll5()
196 		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);  in clock_set_pll5()
208 	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);  in clock_set_pll5()
216 	struct sunxi_ccm_reg * const ccm =  in clock_set_mipi_pll()  local
250 	       CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);  in clock_set_mipi_pll()
257 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll10()  local
262 		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);  in clock_set_pll10()
269 	       &ccm->pll10_cfg);  in clock_set_pll10()
271 	while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))  in clock_set_pll10()
281 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll11()  local
285 		writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);  in clock_set_pll11()
289 	       CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);  in clock_set_pll11()
291 	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)  in clock_set_pll11()
298 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll3()  local
300 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
310 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll6()  local
312 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()
320 	struct sunxi_ccm_reg *const ccm =  in clock_get_mipi_pll()  local
322 	uint32_t rval = readl(&ccm->mipi_pll_cfg);  in clock_get_mipi_pll()