22 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
30 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
31 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);  in clock_init_safe()
37 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
39 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);  in clock_init_safe()
41 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
43 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
44 	setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);  in clock_init_safe()
51 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
58 	       &ccm->apb1_clk_div_cfg);  in clock_init_uart()
61 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
67 	struct sunxi_ccm_reg *const ccm =  in clock_twi_onoff()  local
72 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
75 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
123 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
159 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
167 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
170 	writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);  in clock_set_pll1()
178 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
185 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3()  local
189 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
195 	       CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);  in clock_set_pll3()
200 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll3()  local
202 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
209 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll5p()  local
211 	uint32_t rval = readl(&ccm->pll5_cfg);  in clock_get_pll5p()
220 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll6()  local
222 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()