4  * (C) Copyright 2007-2012
10  * SPDX-License-Identifier:	GPL-2.0+
30 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
31 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);  in clock_init_safe()
37 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
39 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);  in clock_init_safe()
41 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
43 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
44 	setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);  in clock_init_safe()
58 	       &ccm->apb1_clk_div_cfg);  in clock_init_uart()
61 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
62 		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));  in clock_init_uart()
72 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
75 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
82 #define PLL1_CFG(N, K, M, P)	( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \  argument
93 				 (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
122 	int axi, ahb, apb0;  in clock_set_pll1()  local
136 	ahb = DIV_ROUND_UP(hz/axi, 204000000);	/* Max 250MHz */  in clock_set_pll1()
139 	printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);  in clock_set_pll1()
142 	axi = axi - 1;  in clock_set_pll1()
143 	if (ahb > 4)  in clock_set_pll1()
144 		ahb = 3;  in clock_set_pll1()
145 	else if (ahb > 2)  in clock_set_pll1()
146 		ahb = 2;  in clock_set_pll1()
147 	else if (ahb > 1)  in clock_set_pll1()
148 		ahb = 1;  in clock_set_pll1()
150 		ahb = 0;  in clock_set_pll1()
152 	apb0 = apb0 - 1;  in clock_set_pll1()
159 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
164 	       ahb << AHB_DIV_SHIFT |  in clock_set_pll1()
167 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
170 	writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);  in clock_set_pll1()
175 	       ahb << AHB_DIV_SHIFT |  in clock_set_pll1()
178 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
189 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
193 	/* PLL3 rate = 3000000 * m */  in clock_set_pll3()
195 	       CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);  in clock_set_pll3()
202 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
203 	int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);  in clock_get_pll3()  local
204 	return 3000000 * m;  in clock_get_pll3()
211 	uint32_t rval = readl(&ccm->pll5_cfg);  in clock_get_pll5p()
222 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()