49 		.virt = 0x0UL,
50 		.phys = 0x0UL,
51 		.size = 0x40000000UL,
56 		.virt = 0x40000000UL,
57 		.phys = 0x40000000UL,
58 		.size = 0x80000000UL,
63 		0,
102 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);  in gpio_init()
130 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);  in gpio_init()
141 	return 0;  in gpio_init()
151 	return 0;  in spl_board_load_image()
153 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
164 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);  in s_init()
169 	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));  in s_init()
170 	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;  in s_init()
171 	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));  in s_init()
179 	if (version == 0x1650)  in s_init()
180 		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);  in s_init()
181 	else /* 0x1661 ? */  in s_init()
182 		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);  in s_init()
184 	if (version != 0x1667)  in s_init()
185 		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);  in s_init()
187 	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */  in s_init()
188 	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */  in s_init()
194 		"mrc p15, 0, r0, c1, c0, 1\n"  in s_init()
196 		"mcr p15, 0, r0, c1, c0, 1\n"  in s_init()
225 	 * signature is expected to be found in memory at the address 0x0004  in spl_boot_device()
242 	boot_source = readb(SPL_ADDR + 0x28);  in spl_boot_device()