Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:spi
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
12 ---help---
24 ---help---
26 as the original A10 (mach-sun4i).
30 ---help---
37 ---help---
40 not have official open-source DRAM initialization code, but can
46 ---help---
48 have only 16-bit memory buswidth.
52 ---help---
54 32-bit memory buswidth.
71 bool "sun4i (Allwinner A10)"
206 ---help---
207 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
209 blob relies on this information to load and execute U-Boot.
210 Only needed on 64-bit Allwinner boards so far when using boot0.
217 ---help---
218 Insert some ARM32 code at the very beginning of the U-Boot binary
223 This allows both the SPL and the U-Boot proper to be entered in
245 ---help---
252 ---help---
260 ---help---
261 This option is only for the DDR2 memory chip which is co-packaged in
271 ---help---
282 ---help---
283 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
285 (for DDR3-1600) are 312 to 792.
291 ---help---
304 ---help---
313 ---help---
321 ---help---
327 ---help---
338 ---help---
342 means that the delay is 5 quarter-cycles for one lane (1.25
343 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
354 ---help---
359 ---help---
363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
364 ---help---
365 Use the timings of the standard JEDEC DDR3-1066F speed bin for
366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
368 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
369 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
370 that down binning to DDR3-1066F is supported (because DDR3-1066F
371 uses a bit faster timings than DDR3-1333H).
374 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
375 ---help---
378 DDR3-800E, DDR3-1066G or DDR3-1333J.
388 ---help---
389 Set the dram odt correction value (range -255 - 255). In allwinner
390 fex files, this option is found in bits 8-15 of the u32 odt_en variable
405 default "sun4i" if MACH_SUN4I
422 ---help---
424 console. Primarily useful only for low level u-boot debugging on
433 ---help---
435 sub-optimal settings for newer kernels, only enable if needed.
448 ---help---
456 ---help---
462 ---help---
468 ---help---
474 ---help---
481 ---help---
487 ---help---
492 default -1
493 ---help---
495 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
501 ---help---
510 ---help---
517 ---help---
524 ---help---
532 ---help---
541 ---help---
547 ---help---
555 ---help---
565 ---help---
572 ---help---
580 ---help---
590 ---help---
599 ---help---
604 bool "Enable support for gpio-s on axp PMICs"
606 ---help---
618 ---help---
627 ---help---
634 ---help---
641 ---help---
650 ---help---
660 ---help---
668 ---help---
675 ---help---
679 Also see: http://linux-sunxi.org/LCD
685 ---help---
686 Select LCD panel display clock phase shift, range 0-3.
692 ---help---
700 ---help---
708 ---help---
717 ---help---
725 ---help---
733 ---help---
741 ---help---
749 ---help---
772 ---help---
780 ---help---
792 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
795 ---help---
799 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
803 ---help---
811 ---help---
818 ---help---
835 ---help---
848 bool "Support for SPI Flash on Allwinner SoCs in SPL"
851 Enable support for SPI Flash. This option allows SPL to read from
852 sunxi SPI Flash. It uses the same method as the boot ROM, so does