Lines Matching +full:lcd +full:- +full:controller
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
12 ---help---
24 ---help---
26 as the original A10 (mach-sun4i).
30 ---help---
37 ---help---
38 Select this for sunxi SoCs which uses a DRAM controller like the
39 DesignWare controller used in H3, mainly SoCs after H3, which do
40 not have official open-source DRAM initialization code, but can
46 ---help---
47 Select this for sunxi SoCs with DesignWare DRAM controller and
48 have only 16-bit memory buswidth.
52 ---help---
53 Select this for sunxi SoCs with DesignWare DRAM controller with
54 32-bit memory buswidth.
206 ---help---
207 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
209 blob relies on this information to load and execute U-Boot.
210 Only needed on 64-bit Allwinner boards so far when using boot0.
217 ---help---
218 Insert some ARM32 code at the very beginning of the U-Boot binary
223 This allows both the SPL and the U-Boot proper to be entered in
245 ---help---
252 ---help---
260 ---help---
261 This option is only for the DDR2 memory chip which is co-packaged in
271 ---help---
282 ---help---
283 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
285 (for DDR3-1600) are 312 to 792.
291 ---help---
304 ---help---
313 ---help---
321 ---help---
322 Set the dram controller emr1 value.
327 ---help---
328 Set the dram controller tpr3 parameter. This parameter configures
338 ---help---
339 Set the dram controller dqs_gating_delay parmeter. Each byte
342 means that the delay is 5 quarter-cycles for one lane (1.25
343 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
354 ---help---
359 ---help---
363 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
364 ---help---
365 Use the timings of the standard JEDEC DDR3-1066F speed bin for
366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
368 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
369 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
370 that down binning to DDR3-1066F is supported (because DDR3-1066F
371 uses a bit faster timings than DDR3-1333H).
374 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
375 ---help---
378 DDR3-800E, DDR3-1066G or DDR3-1333J.
388 ---help---
389 Set the dram odt correction value (range -255 - 255). In allwinner
390 fex files, this option is found in bits 8-15 of the u32 odt_en variable
422 ---help---
424 console. Primarily useful only for low level u-boot debugging on
433 ---help---
435 sub-optimal settings for newer kernels, only enable if needed.
448 ---help---
456 ---help---
462 ---help---
468 ---help---
474 ---help---
481 ---help---
487 ---help---
492 default -1
493 ---help---
495 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
501 ---help---
510 ---help---
517 ---help---
524 ---help---
532 ---help---
541 ---help---
547 ---help---
551 bool "Enable I2C/TWI controller 0"
555 ---help---
556 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
562 bool "Enable I2C/TWI controller 1"
565 ---help---
569 bool "Enable I2C/TWI controller 2"
572 ---help---
577 bool "Enable I2C/TWI controller 3"
580 ---help---
586 bool "Enable the PRCM I2C/TWI controller"
590 ---help---
591 Set this to y to enable the I2C controller which is part of the PRCM.
596 bool "Enable I2C/TWI controller 4"
599 ---help---
604 bool "Enable support for gpio-s on axp PMICs"
606 ---help---
610 bool "Enable graphical uboot console on HDMI, LCD or VGA"
618 ---help---
619 Say Y here to add support for using a cfb console on the HDMI, LCD
627 ---help---
634 ---help---
638 bool "VGA via LCD controller support"
641 ---help---
643 LCD interface driving a VGA connector, such as found on the
647 bool "Force sync active high for VGA via LCD controller support"
650 ---help---
657 string "LCD panel power enable pin"
660 ---help---
668 ---help---
672 string "LCD panel timing details"
675 ---help---
676 LCD panel timing details string, leave empty if there is no LCD panel.
679 Also see: http://linux-sunxi.org/LCD
682 int "LCD panel display clock phase"
685 ---help---
686 Select LCD panel display clock phase shift, range 0-3.
689 string "LCD panel power enable pin"
692 ---help---
693 Set the power enable pin for the LCD panel. This takes a string in the
697 string "LCD panel reset pin"
700 ---help---
701 Set the reset pin for the LCD panel. This takes a string in the format
705 string "LCD panel backlight enable pin"
708 ---help---
709 Set the backlight enable pin for the LCD panel. This takes a string in the
714 string "LCD panel backlight pwm pin"
717 ---help---
718 Set the backlight pwm pin for the LCD panel. This takes a string in the
722 bool "LCD panel backlight pwm is inverted"
725 ---help---
729 bool "LCD panel needs to be configured via i2c"
733 ---help---
734 Say y here if the LCD panel needs to be configured via i2c. This
735 will add a bitbang i2c controller using gpios to talk to the LCD.
738 string "LCD panel i2c interface SDA pin"
741 ---help---
742 Set the SDA pin for the LCD i2c interface. This takes a string in the
746 string "LCD panel i2c interface SCL pin"
749 ---help---
750 Set the SCL pin for the LCD i2c interface. This takes a string in the
772 ---help---
778 prompt "LCD panel support"
780 ---help---
781 Select which type of LCD panel to support.
784 bool "Generic parallel interface LCD panel"
788 bool "Generic lvds interface LCD panel"
792 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
795 ---help---
796 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
799 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
803 ---help---
804 Select this for eDP LCD panels with 4 lanes running at 1.62G,
808 bool "Hitachi tx18d42vm LCD panel"
811 ---help---
812 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
815 bool "tl059wv5c0 LCD panel"
818 ---help---
835 ---help---