Lines Matching full:dram

38 	Select this for sunxi SoCs which uses a DRAM controller like the
40 	not have official open-source DRAM initialization code, but can
41 	use modified H3 DRAM initialization code.
47 	Select this for sunxi SoCs with DesignWare DRAM controller and
53 	Select this for sunxi SoCs with DesignWare DRAM controller with
237 	prompt "DRAM Type and Timing"
268 	int "sunxi dram type"
272 	Set the dram type, 3: DDR3, 7: LPDDR3
275 	int "sunxi dram clock speed"
283 	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
297 	int "sunxi dram zq value"
305 	Set the dram zq value.
308 	bool "sunxi dram odt enable"
314 	Select this to enable dram odt (on die termination).
318 	int "sunxi dram emr1 value"
322 	Set the dram controller emr1 value.
325 	hex "sunxi dram tpr3 value"
328 	Set the dram controller tpr3 parameter. This parameter configures
332 	configuring this parameter increases reliability at high DRAM
336 	hex "sunxi dram dqs_gating_delay value"
339 	Set the dram controller dqs_gating_delay parmeter. Each byte
348 	is usually good enough, unless running at really high DRAM
352 	prompt "sunxi dram timings"
360 	The same DRAM timings as in the Allwinner boot0 bootloader.
369 	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
386 	int "sunxi dram odt correction value"
389 	Set the dram odt correction value (range -255 - 255). In allwinner
391 	in the [dram] section. When bit 31 of the odt_en variable is set