2  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4  * SPDX-License-Identifier:	GPL-2.0+
25 #include <dt-bindings/reset/altr,rst-mgr.h>
63 	clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,  in dwmac_deassert_reset()
74 		return -EINVAL;  in dwmac_phymode_to_modereg()
91 	return -EINVAL;  in dwmac_phymode_to_modereg()
96 	const void *fdt = gd->fdt_blob;  in socfpga_eth_reset()
117 						     "#reset-cells", 1, 0,  in socfpga_eth_reset()
124 		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);  in socfpga_eth_reset()
127 			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);  in socfpga_eth_reset()
182 		return -EINVAL;  in socfpga_fpga_id()
191 		return -EINVAL;  in socfpga_fpga_id()
207 		SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));  in print_cpuinfo()
220 	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;  in arch_misc_init()
230  * Convert all NIC-301 AMBA slaves from secure to non-secure
234 	writel(0x1, &nic301_regs->lwhps2fpgaregs);  in socfpga_nic301_slave_ns()
235 	writel(0x1, &nic301_regs->hps2fpgaregs);  in socfpga_nic301_slave_ns()
236 	writel(0x1, &nic301_regs->acp);  in socfpga_nic301_slave_ns()
237 	writel(0x1, &nic301_regs->rom);  in socfpga_nic301_slave_ns()
238 	writel(0x1, &nic301_regs->ocram);  in socfpga_nic301_slave_ns()
239 	writel(0x1, &nic301_regs->sdrdata);  in socfpga_nic301_slave_ns()
255 	writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);  in arch_early_init_r()
258 		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);  in arch_early_init_r()
266 	 * U-Boot : configure private timer, global timer and cpu component  in arch_early_init_r()
269 	setbits_le32(&scu_regs->sacr, 0xfff);  in arch_early_init_r()
273 	writel(0x2, &nic301_regs->remap);  in arch_early_init_r()
275 	writel(0x1, &nic301_regs->remap);	/* remap.mpuzero */  in arch_early_init_r()
276 	writel(0x1, &pl310->pl310_addr_filter_start);  in arch_early_init_r()
298 	u32 val = readl(&sdr_ctrl->static_cfg) | applymask;  in socfpga_sdram_apply_static_cfg()
303 	 * SDRAM. Luckily for us, we can abuse i-cache here to help us  in socfpga_sdram_apply_static_cfg()
305 	 * that the code is in one full i-cache line by branching past  in socfpga_sdram_apply_static_cfg()
306 	 * it and back. Once it is in the i-cache, we execute the core  in socfpga_sdram_apply_static_cfg()
309 	 * The code below uses 7 instructions, while the Cortex-A9 has  in socfpga_sdram_apply_static_cfg()
310 	 * 32-byte cachelines, thus the limit is 8 instructions total.  in socfpga_sdram_apply_static_cfg()
321 	: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");  in socfpga_sdram_apply_static_cfg()
333 		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);  in do_bridge()
335 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);  in do_bridge()
336 		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);  in do_bridge()
337 		writel(iswgrp_handoff[1], &nic301_regs->remap);  in do_bridge()
340 		writel(0, &sysmgr_regs->fpgaintfgrp_module);  in do_bridge()
341 		writel(0, &sdr_ctrl->fpgaport_rst);  in do_bridge()
343 		writel(0, &reset_manager_base->brg_mod_reset);  in do_bridge()
344 		writel(1, &nic301_regs->remap);  in do_bridge()
356 	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
357 	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"