Lines Matching +full:0 +full:x01e00000

23 #define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
30 	u32	dram_timing4;	/* 0x10 */
35 	u32	dram_addrw;	/* 0x2c */
36 	u32	dram_if_width;	/* 0x30 */
40 	u32	sbe_count;	/* 0x40 */
44 	u32	drop_addr;	/* 0x50 */
48 	u32	ctrl_width;	/* 0x60 */
52 	u32	rfifo_cmap;	/* 0x70 */
56 	u32	fpgaport_rst;	/* 0x80 */
60 	u32	prot_rule_addr;	/* 0x90 */
65 	u32	mp_priority;	/* 0xac */
66 	u32	mp_weight0;	/* 0xb0 */
70 	u32	mp_pacing0;	/* 0xc0 */
74 	u32	mp_threshold0;	/* 0xd0 */
78 	u32	phy_ctrl0;	/* 0x150 */
222 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
224 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
226 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
228 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
230 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
232 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
234 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
236 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
237 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
238 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
241 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
243 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
245 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
247 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
249 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
250 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
251 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
254 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
256 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
258 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
260 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
261 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
262 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
265 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
267 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
269 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
271 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
272 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
273 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
276 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
278 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
279 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
280 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
283 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
284 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
285 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
288 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
290 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
292 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
293 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
294 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
296 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
297 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
299 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
300 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
302 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
303 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
305 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
308 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
310 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
311 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
312 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
314 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
315 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
317 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
318 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
320 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
321 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
323 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
324 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
326 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
327 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
329 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
330 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
332 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
333 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
336 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
337 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
338 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
341 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
342 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
343 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
345 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
346 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
348 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
349 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
352 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
353 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
354 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
356 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
357 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
359 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
360 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
362 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
363 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
366 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
367 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
368 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
370 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
371 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
373 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
374 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
377 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
380 0xffffffff
383 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
386 0xffffffff
389 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
392 0x0000ffff
394 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
395 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
400  (((x) << 12) & 0xfffff000)
402  (((x) << 10) & 0x00000c00)
404  (((x) << 6) & 0x000000c0)
406  (((x) << 8) & 0x00000100)
408  (((x) << 9) & 0x00000200)
410  (((x) << 4) & 0x00000030)
412  (((x) << 2) & 0x0000000c)
414  (((x) << 0) & 0x00000003)
418  (((x) << 12) & 0xfffff000)
420  (((x) << 0) & 0x00000fff)
423  (((x) << 0) & 0x00000fff)
426 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
427 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
428 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
430 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
431 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004