Lines Matching refs:sys_reg
30 u32 sys_reg = readl(reg); in rockchip_sdram_size() local
32 u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) in rockchip_sdram_size()
35 dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; in rockchip_sdram_size()
36 debug("%s %x %x\n", __func__, (u32)reg, sys_reg); in rockchip_sdram_size()
38 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
40 cs0_col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); in rockchip_sdram_size()
42 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); in rockchip_sdram_size()
48 SYS_REG1_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg >> in rockchip_sdram_size()
53 cs0_row = 13 + (sys_reg >> in rockchip_sdram_size()
60 SYS_REG1_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg >> in rockchip_sdram_size()
65 cs1_row = 13 + (sys_reg >> in rockchip_sdram_size()
73 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
75 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & in rockchip_sdram_size()
78 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & in rockchip_sdram_size()
80 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & in rockchip_sdram_size()
83 dbw = (sys_reg >> SYS_REG_DBW_SHIFT(ch)) & in rockchip_sdram_size()