20 #define PERI_GRF_BASE			0xff000000
21 #define PERI_GRF_PERI_CON1		0x0004
23 #define CORE_GRF_BASE			0xff040000
24 #define CORE_GRF_CACHE_PERI_ADDR_START	0x0024
25 #define CORE_GRF_CACHE_PERI_ADDR_END	0x0028
26 #define CORE_GRF_MCU_CACHE_MISC		0x002c
28 #define PERI_GRF_BASE			0xff000000
29 #define PERI_GRF_USBPHY_CON0		0x0050
31 #define PERI_SGRF_BASE			0xff070000
32 #define PERI_SGRF_FIREWALL_CON0		0x0020
33 #define PERI_SGRF_FIREWALL_CON1		0x0024
34 #define PERI_SGRF_FIREWALL_CON2		0x0028
35 #define PERI_SGRF_FIREWALL_CON3		0x002c
36 #define PERI_SGRF_FIREWALL_CON4		0x0030
37 #define PERI_SGRF_SOC_CON3		0x00bc
39 #define CORE_SGRF_BASE			0xff076000
40 #define CORE_SGRF_FIREWALL_CON0		0x0020
41 #define CORE_SGRF_FIREWALL_CON1		0x0024
42 #define CORE_SGRF_FIREWALL_CON2		0x0028
43 #define CORE_SGRF_FIREWALL_CON3		0x002c
44 #define CORE_SGRF_FIREWALL_CON4		0x0030
45 #define CORE_SGRF_CPU_CTRL_CON		0x0040
46 #define CORE_SGRF_HPMCU_BOOT_ADDR	0x0044
48 #define PMU_SGRF_BASE			0xff080000
51 #define QOS_CPU_BASE			0xff110000
52 #define QOS_CRYPTO_BASE			0xff120000
53 #define QOS_DECOM_BASE			0xff120080
54 #define QOS_DMAC_BASE			0xff120100
55 #define QOS_EMMC_BASE			0xff120180
56 #define QOS_FSPI_BASE			0xff120200
57 #define QOS_IVE_RD_BASE			0xff120280
58 #define QOS_IVE_WR_BASE			0xff120300
59 #define QOS_USB_BASE			0xff120380
60 #define QOS_ISP_BASE			0xff130000
61 #define QOS_SDMMC0_BASE			0xff130080
62 #define QOS_VICAP_BASE			0xff130100
63 #define QOS_NPU_BASE			0xff140000
64 #define QOS_VENC_BASE			0xff150000
65 #define QOS_VEPU_PP_BASE		0xff150080
66 #define QOS_MAC_BASE			0xff160000
67 #define QOS_RGA_RD_BASE			0xff160080
68 #define QOS_RGA_WR_BASE			0xff160100
69 #define QOS_SDIO_BASE			0xff160280
70 #define QOS_VOP_BASE			0xff160300
72 #define QOS_PRIORITY			0x0008
73 #define QOS_MODE			0x000c
74 #define QOS_BANDWIDTH			0x0010
75 #define QOS_SATURATION			0x0014
76 #define QOS_EXTCONTROL			0x0018
79 #define SHAPING_CPU_BASE		0xff110080
80 #define SHAPING_DECOM_BASE		0xff110400
81 #define SHAPING_IVE_RD_BASE		0xff120480
82 #define SHAPING_IVE_WR_BASE		0xff120500
83 #define SHAPING_ISP_BASE		0xff130180
84 #define SHAPING_VICAP_BASE		0xff130200
85 #define SHAPING_NPU_BASE		0xff140080
86 #define SHAPING_VENC_BASE		0xff150100
87 #define SHAPING_VEPU_PP_BASE		0xff150180
88 #define SHAPING_RGA_RD_BASE		0xff160380
89 #define SHAPING_RGA_WR_BASE		0xff160400
90 #define SHAPING_VOP_BASE		0xff160580
92 #define SHAPING_NBPKTMAX		0x0008
94 #define FW_DDR_BASE			0xff900000
95 #define FW_DDR_MST3_REG			0x4c
96 #define FW_SHRM_BASE			0xff910000
97 #define FW_SHRM_MST1_REG		0x44
99 #define PMU_BASE			0xff300000
100 #define PMU_BIU_IDLE_ST			0x00d8
102 #define CRU_BASE			0xff3b0000
103 #define CRU_GLB_RST_CON			0x0c10
104 #define CRU_PVTPLL0_CON0_L		0x1000
105 #define CRU_PVTPLL0_CON1_L		0x1008
106 #define CRU_PVTPLL1_CON0_L		0x1030
107 #define CRU_PVTPLL1_CON1_L		0x1038
109 #define CORECRU_BASE			0xff3b8000
110 #define CORECRU_CORESOFTRST_CON01	0xa04
112 #define USBPHY_APB_BASE			0xff3e0000
113 #define USBPHY_FSLS_DIFF_RECEIVER	0x0100
115 #define GPIO0_IOC_BASE			0xFF388000
116 #define GPIO1_IOC_BASE			0xFF538000
117 #define GPIO2_IOC_BASE			0xFF548000
118 #define GPIO3_IOC_BASE			0xFF558000
119 #define GPIO4_IOC_BASE			0xFF568000
121 #define GPIO3A_IOMUX_SEL_L		0x0040
122 #define GPIO3A_IOMUX_SEL_H		0x0044
124 #define GPIO4A_IOMUX_SEL_L		0x000
125 #define GPIO4A_IOMUX_SEL_H		0x004
126 #define GPIO4B_IOMUX_SEL_L		0x008
128 #define GPIO4_IOC_GPIO4B_DS0		0x0030
130 /* OS_REG1[2:0]: chip ver */
131 #define CHIP_VER_REG			0xff020204
132 #define CHIP_VER_MSK			0x7
134 #define ROM_VER_REG			0xffff4ffc
135 #define ROM_V2				0x30303256
140 #define UART0_RX_M0_OFFSET		0
149 #define UART0_RX_M1_OFFSET		0
150 #define UART0_RX_M1_ADDR		(GPIO2_IOC_BASE + 0x28)
154 #define UART0_TX_M1_ADDR		(GPIO2_IOC_BASE + 0x28)
158 #define UART0_RX_M2_OFFSET		0
168 #define UART1_RX_M0_OFFSET		0
169 #define UART1_RX_M0_ADDR		(GPIO1_IOC_BASE + 0x4)
178 #define UART1_RX_M1_ADDR		(GPIO2_IOC_BASE + 0x24)
181 #define UART1_TX_M1_OFFSET		0
182 #define UART1_TX_M1_ADDR		(GPIO2_IOC_BASE + 0x24)
187 #define UART1_RX_M2_ADDR		(GPIO4_IOC_BASE + 0x4)
191 #define UART1_TX_M2_ADDR		(GPIO4_IOC_BASE + 0x4)
197 #define UART2_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x40)
201 #define UART2_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x40)
206 #define UART2_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x8)
210 #define UART2_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x8)
219 #define UART3_TX_M0_OFFSET		0
225 #define UART3_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x18)
228 #define UART3_TX_M1_OFFSET		0
229 #define UART3_TX_M1_ADDR		(GPIO2_IOC_BASE + 0x18)
234 #define UART4_RX_M0_OFFSET		0
235 #define UART4_RX_M0_ADDR		(GPIO1_IOC_BASE + 0x8)
239 #define UART4_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x8)
243 #define UART4_RX_M1_OFFSET		0
244 #define UART4_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x14)
248 #define UART4_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x14)
254 #define UART5_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x44)
258 #define UART5_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x44)
263 #define UART5_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x18)
267 #define UART5_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x18)
271 #define UART5_RX_M2_OFFSET		0
272 #define UART5_RX_M2_ADDR		(GPIO3_IOC_BASE + 0x58)
276 #define UART5_TX_M2_ADDR		(GPIO4_IOC_BASE + 0x54)
288 /* UART 0 */  in board_debug_uart_init()
289 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4a0000)  in board_debug_uart_init()
292 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
295 	set_uart_iomux_rx(0, 0);  in board_debug_uart_init()
296 	set_uart_iomux_tx(0, 0);  in board_debug_uart_init()
301 	set_uart_iomux_rx(0, 1);  in board_debug_uart_init()
302 	set_uart_iomux_tx(0, 1);  in board_debug_uart_init()
307 	set_uart_iomux_rx(0, 2);  in board_debug_uart_init()
308 	set_uart_iomux_tx(0, 2);  in board_debug_uart_init()
312 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4b0000)  in board_debug_uart_init()
315 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
318 	set_uart_iomux_rx(1, 0);  in board_debug_uart_init()
319 	set_uart_iomux_tx(1, 0);  in board_debug_uart_init()
334 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4c0000)  in board_debug_uart_init()
337 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
340 	set_uart_iomux_rx(2, 0);  in board_debug_uart_init()
341 	set_uart_iomux_tx(2, 0);  in board_debug_uart_init()
351 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4d0000)  in board_debug_uart_init()
353 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
356 	set_uart_iomux_rx(3, 0);  in board_debug_uart_init()
357 	set_uart_iomux_tx(3, 0);  in board_debug_uart_init()
366 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4e0000)  in board_debug_uart_init()
368 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
371 	set_uart_iomux_rx(4, 0);  in board_debug_uart_init()
372 	set_uart_iomux_tx(4, 0);  in board_debug_uart_init()
381 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff4f0000)  in board_debug_uart_init()
383 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
386 	set_uart_iomux_rx(5, 0);  in board_debug_uart_init()
387 	set_uart_iomux_tx(5, 0);  in board_debug_uart_init()
407 	/* Save chip version to OS_REG1[2:0] */  in arch_cpu_init()
414 	writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON0);  in arch_cpu_init()
415 	writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON1);  in arch_cpu_init()
416 	writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON2);  in arch_cpu_init()
417 	writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON3);  in arch_cpu_init()
418 	writel(0xffff0000, PERI_SGRF_BASE + PERI_SGRF_FIREWALL_CON4);  in arch_cpu_init()
419 	writel(0x000f0000, PERI_SGRF_BASE + PERI_SGRF_SOC_CON3);  in arch_cpu_init()
420 	writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON0);  in arch_cpu_init()
421 	writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON1);  in arch_cpu_init()
422 	writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON2);  in arch_cpu_init()
423 	writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON3);  in arch_cpu_init()
424 	writel(0xffff0000, CORE_SGRF_BASE + CORE_SGRF_FIREWALL_CON4);  in arch_cpu_init()
425 	writel(0x00030002, CORE_SGRF_BASE + CORE_SGRF_CPU_CTRL_CON);  in arch_cpu_init()
426 	writel(0x20000000, PMU_SGRF_BASE);  in arch_cpu_init()
429 	writel(0x00000000, FW_DDR_BASE + FW_DDR_MST3_REG);  in arch_cpu_init()
430 	writel(0xff00ffff, FW_SHRM_BASE + FW_SHRM_MST1_REG);  in arch_cpu_init()
433 	if ((readl(GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L) & 0x70) == 0x20)  in arch_cpu_init()
434 		writel(0x3f000700, GPIO4_IOC_BASE + GPIO4_IOC_GPIO4B_DS0);  in arch_cpu_init()
442 	writel(0x01ff01d1, PERI_GRF_BASE + PERI_GRF_USBPHY_CON0);  in arch_cpu_init()
443 	writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);  in arch_cpu_init()
446 	writel(0x2000200, PERI_GRF_BASE + PERI_GRF_PERI_CON1);  in arch_cpu_init()
447 	writel(0x400040, CRU_BASE + CRU_GLB_RST_CON);  in arch_cpu_init()
457 	writel(0xffff0018, CRU_BASE + CRU_PVTPLL0_CON1_L);  in arch_cpu_init()
458 	writel(0x00030003, CRU_BASE + CRU_PVTPLL0_CON0_L);  in arch_cpu_init()
459 	writel(0xffff0018, CRU_BASE + CRU_PVTPLL1_CON1_L);  in arch_cpu_init()
460 	writel(0x00030003, CRU_BASE + CRU_PVTPLL1_CON0_L);  in arch_cpu_init()
473 	writel(0x4, SHAPING_NPU_BASE + SHAPING_NBPKTMAX);  in arch_cpu_init()
476 	writel(0x303, QOS_VENC_BASE + QOS_PRIORITY);  in arch_cpu_init()
480 	writel(0xfff01110, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L);  in arch_cpu_init()
481 	writel(0xffff1111, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H);  in arch_cpu_init()
486 	writel(0x0f000700, GPIO4_IOC_BASE + 0x0030);  in arch_cpu_init()
487 	writel(0xff002200, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in arch_cpu_init()
488 	writel(0x0f0f0202, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in arch_cpu_init()
489 	writel(0x00ff0022, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in arch_cpu_init()
492 	writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_L);  in arch_cpu_init()
493 	writel(0xffff1111, GPIO4_IOC_BASE + GPIO4A_IOMUX_SEL_H);  in arch_cpu_init()
494 	writel(0x00ff0011, GPIO4_IOC_BASE + GPIO4B_IOMUX_SEL_L);  in arch_cpu_init()
498 	return 0;  in arch_cpu_init()
505 	writel(0xff000, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_START);  in spl_fit_standalone_release()
506 	writel(0xffc00, CORE_GRF_BASE + CORE_GRF_CACHE_PERI_ADDR_END);  in spl_fit_standalone_release()
508 	writel(0x1e001e, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);  in spl_fit_standalone_release()
512 	writel(0x1e0000, CORECRU_BASE + CORECRU_CORESOFTRST_CON01);  in spl_fit_standalone_release()
514 	return 0;  in spl_fit_standalone_release()
519 	writel(0x00080008, CORE_GRF_BASE + CORE_GRF_MCU_CACHE_MISC);  in rk_meta_process()
528 	if (!run_command("blk dev mmc 1", 0) &&  in rk_board_scan_bootdev()
529 	    !run_command("rkimgtest mmc 1", 0)) {  in rk_board_scan_bootdev()
533 		run_command("blk dev mtd 2", 0);  in rk_board_scan_bootdev()
540 	return 0;  in rk_board_scan_bootdev()
548 #define	PAGE_SWITCH			0x1f
549 #define	DISABLE_APS_REG			0x12
550 #define	DISABLE_APS_VAL			0x4824
551 #define	PHYAFE_PDCW_REG			0x1c
552 #define	PHYAFE_PDCW_VAL			0x8880
553 #define	PD_ANALOG_REG			0x0
554 #define PD_ANALOG_VAL			0x3900
573 	if (fdt_stringlist_search(fdt, gmac_node, "status", "disabled") >= 0) {  in rk_board_fdt_pwrdn_gmac()
575 		miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0100);  in rk_board_fdt_pwrdn_gmac()
579 		miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0600);  in rk_board_fdt_pwrdn_gmac()
582 		/* switch to page 0 */  in rk_board_fdt_pwrdn_gmac()
583 		miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0000);  in rk_board_fdt_pwrdn_gmac()
594 	return 0;  in rk_board_fdt_pwrdn_gmac()
604 	return 0;  in rk_board_fdt_fixup()