Lines Matching full:400000000
1152 * rate[1] = <400000000>; // ACLK_RKVDEC_PRE in rk_board_fdt_fixup()
1153 * rate[2] = <400000000>; // CLK_RKVDEC_CORE in rk_board_fdt_fixup()
1154 * rate[5] = <400000000>; // PLL_CPLL in rk_board_fdt_fixup()
1160 pp[1] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1161 pp[2] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1162 pp[5] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1186 pp[0] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1188 pp[2] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1189 pp[3] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1190 pp[4] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1198 pp[0] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1199 pp[1] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1200 pp[2] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()
1201 pp[3] = cpu_to_fdt32(400000000); in rk_board_fdt_fixup()