23 #define FIREWALL_DDR_BASE	0xfef00000
24 #define FW_DDR_MST3_REG		0x2c	/* usb */
25 #define FW_DDR_MST4_REG		0x30	/* emmc */
26 #define FW_DDR_MST5_REG		0x34	/* fspi */
27 #define FW_DDR_MST6_REG		0x38	/* sdmmc mcu */
28 #define FW_DDR_CON_REG		0x80
30 #define PMU_GRF_BASE		0xff010000
31 #define PMU_GRF_SOC_CON9	0x0124
33 #define SYS_GRF_BASE		0xff030000
34 #define SYS_GRF_SOC_CON5	0x0414
35 #define SYS_GRF_SOC_CON6	0x0418
37 #define PERI_GRF_BASE		0xff040000
38 #define PERI_GRF_AUDIO_CON	0x0070
40 #define PIPEPHY_GRF_BASE	0xff098000
41 #define PIPEPHY_PIPE_CON5	0x0014
43 #define TOP_CRU_BASE		0xff100000
44 #define TOP_CRU_GATE_CON23	0x035c
45 #define TOP_CRU_SOFTRST_CON23	0x045c
46 #define TOP_CRU_CM0_GATEMASK	0x0680
48 #define PMU0_CRU_BASE		0xff110000
50 #define PMU1_CRU_BASE		0xff118000
51 #define PMU1_CRU_GATE_CON02	0x0188
52 #define PMU1_CRU_SOFTRST_CON02	0x0208
53 #define PMU1_CRU_CM0_GATEMASK	0x0420
55 #define PMU_BASE_ADDR		0xff258000
56 #define PMU2_BIU_IDLE_SFTCON0	0x110
57 #define PMU2_BIU_IDLE_ACK_STS0	0x120
58 #define PMU2_BIT_IDLE_STS0	0x128
59 #define PMU2_PWR_GATE_SFTCON0	0x210
60 #define PMU2_PWR_GATE_STS0	0x230
61 #define PMU2_MEM_SD_SFTCON0	0x300
63 #define PD_GPU_DWN_SFTENA	BIT(0)
79 #define CRYPTO_PRIORITY_REG	0xfeeb0108
80 #define DCF_PRIORITY_REG	0xfee10408
81 #define DMA2DDR_PRIORITY_REG	0xfee03808
82 #define DMAC_PRIORITY_REG	0xfeeb0208
83 #define EMMC_PRIORITY_REG	0xfeeb0308
84 #define FSPI_PRIORITY_REG	0xfeeb0408
85 #define GMAC_PRIORITY_REG	0xfee10208
86 #define GPU_PRIORITY_REG	0xfee30008
87 #define ISP_PRIORITY_REG	0xfee70008
88 #define MAC100_PRIORITY_REG	0xfee10308
89 #define MCU_PRIORITY_REG	0xfee10008
90 #define PCIE_PRIORITY_REG	0xfeea0008
91 #define RKDMA_PRIORITY_REG	0xfeeb0508
92 #define SDMMC0_PRIORITY_REG	0xfeeb0608
93 #define SDMMC1_PRIORITY_REG	0xfeeb0708
94 #define USB2_PRIORITY_REG	0xfeeb0808
95 #define USB3_PRIORITY_REG	0xfeea0108
96 #define VICAP_PRIORITY_REG	0xfee70108
97 #define VOP_PRIORITY_REG	0xfee80008
106 		.virt = 0x0UL,
107 		.phys = 0x0UL,
108 		.size = 0xfc000000UL,
112 		.virt = 0xfc000000UL,
113 		.phys = 0xfc000000UL,
114 		.size = 0x04000000UL,
120 		0,
127 #define	GPIO0_IOC_BASE			0xFF080000
128 #define	GPIO1_IOC_BASE			0xFF060000
129 #define	GPIO1A_IOMUX_SEL_L		0x0
130 #define	GPIO1A_IOMUX_SEL_H		0x4
131 #define	GPIO1B_IOMUX_SEL_L		0x8
132 #define	GPIO1_IOC_GPIO1A_DS0		0x200
133 #define	GPIO1_IOC_GPIO1A_DS1		0x204
134 #define	GPIO1_IOC_GPIO1B_DS0		0x210
136 #define	GPIO2_IOC_BASE			0xFF060000
137 #define	GPIO2_IOC_IO_VSEL0		0x300
141 #define	GPIO3_IOC_BASE			0xFF070000
142 #define	GPIO4_IOC_BASE			0xFF070000
147 #define UART0_RX_M0_OFFSET		0
148 #define UART0_RX_M0_ADDR		(GPIO0_IOC_BASE + 0x18)
152 #define UART0_TX_M0_ADDR		(GPIO0_IOC_BASE + 0x18)
157 #define UART0_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x08)
160 #define UART0_TX_M1_OFFSET		0
161 #define UART0_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x0C)
167 #define UART1_RX_M0_ADDR		(GPIO1_IOC_BASE + 0x18)
171 #define UART1_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x18)
176 #define UART1_RX_M1_ADDR		(GPIO4_IOC_BASE + 0x64)
180 #define UART1_TX_M1_ADDR		(GPIO4_IOC_BASE + 0x64)
186 #define UART2_RX_M0_ADDR		(GPIO0_IOC_BASE + 0x10)
189 #define UART2_TX_M0_OFFSET		0
190 #define UART2_TX_M0_ADDR		(GPIO0_IOC_BASE + 0x10)
195 #define UART2_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x40)
198 #define UART2_TX_M1_OFFSET		0
199 #define UART2_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x40)
205 #define UART3_RX_M0_ADDR		(GPIO4_IOC_BASE + 0x6C)
208 #define UART3_TX_M0_OFFSET		0
209 #define UART3_TX_M0_ADDR		(GPIO4_IOC_BASE + 0x6C)
213 #define UART3_RX_M1_OFFSET		0
214 #define UART3_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x50)
218 #define UART3_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x4C)
224 #define UART4_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x58)
227 #define UART4_TX_M0_OFFSET		0
228 #define UART4_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x58)
233 #define UART4_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x1C)
237 #define UART4_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x1C)
243 #define UART5_RX_M0_ADDR		(GPIO1_IOC_BASE + 0xC)
246 #define UART5_TX_M0_OFFSET		0
247 #define UART5_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x10)
252 #define UART5_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x44)
256 #define UART5_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x44)
262 #define UART6_RX_M0_ADDR		(GPIO0_IOC_BASE + 0x14)
266 #define UART6_TX_M0_ADDR		(GPIO0_IOC_BASE + 0x14)
270 #define UART6_RX_M1_OFFSET		0
271 #define UART6_RX_M1_ADDR		(GPIO4_IOC_BASE + 0x68)
275 #define UART6_TX_M1_ADDR		(GPIO4_IOC_BASE + 0x64)
281 #define UART7_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x54)
284 #define UART7_TX_M0_OFFSET		0
285 #define UART7_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x54)
290 #define UART7_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x08)
293 #define UART7_TX_M1_OFFSET		0
294 #define UART7_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x0C)
300 #define UART8_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x48)
304 #define UART8_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x48)
309 #define UART8_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x5C)
312 #define UART8_TX_M1_OFFSET		0
313 #define UART8_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x5C)
319 #define UART9_RX_M0_ADDR		(GPIO4_IOC_BASE + 0x68)
323 #define UART9_TX_M0_ADDR		(GPIO4_IOC_BASE + 0x68)
328 #define UART9_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x50)
332 #define UART9_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x50)
344 /* UART 0 */  in board_debug_uart_init()
345 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff210000)  in board_debug_uart_init()
348 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
351 	set_uart_iomux_rx(0, 0);  in board_debug_uart_init()
352 	set_uart_iomux_tx(0, 0);  in board_debug_uart_init()
357 	set_uart_iomux_rx(0, 1);  in board_debug_uart_init()
358 	set_uart_iomux_tx(0, 1);  in board_debug_uart_init()
361 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff670000)  in board_debug_uart_init()
364 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
367 	set_uart_iomux_rx(1, 0);  in board_debug_uart_init()
368 	set_uart_iomux_tx(1, 0);  in board_debug_uart_init()
377 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff680000)  in board_debug_uart_init()
380 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
383 	set_uart_iomux_rx(2, 0);  in board_debug_uart_init()
384 	set_uart_iomux_tx(2, 0);  in board_debug_uart_init()
393 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)  in board_debug_uart_init()
395 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
398 	set_uart_iomux_rx(3, 0);  in board_debug_uart_init()
399 	set_uart_iomux_tx(3, 0);  in board_debug_uart_init()
408 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6a0000)  in board_debug_uart_init()
410 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
413 	set_uart_iomux_rx(4, 0);  in board_debug_uart_init()
414 	set_uart_iomux_tx(4, 0);  in board_debug_uart_init()
423 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6b0000)  in board_debug_uart_init()
425 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
428 	set_uart_iomux_rx(5, 0);  in board_debug_uart_init()
429 	set_uart_iomux_tx(5, 0);  in board_debug_uart_init()
438 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6c0000)  in board_debug_uart_init()
440 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
443 	set_uart_iomux_rx(6, 0);  in board_debug_uart_init()
444 	set_uart_iomux_tx(6, 0);  in board_debug_uart_init()
453 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6d0000)  in board_debug_uart_init()
455 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
458 	set_uart_iomux_rx(7, 0);  in board_debug_uart_init()
459 	set_uart_iomux_tx(7, 0);  in board_debug_uart_init()
468 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6e0000)  in board_debug_uart_init()
470 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
473 	set_uart_iomux_rx(8, 0);  in board_debug_uart_init()
474 	set_uart_iomux_tx(8, 0);  in board_debug_uart_init()
483 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6f0000)  in board_debug_uart_init()
485 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
488 	set_uart_iomux_rx(9, 0);  in board_debug_uart_init()
489 	set_uart_iomux_tx(9, 0);  in board_debug_uart_init()
504 	writel(0x03180000, TOP_CRU_BASE + TOP_CRU_GATE_CON23);  in fit_standalone_release()
507 	writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);  in fit_standalone_release()
510 	writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);  in fit_standalone_release()
511 	writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);  in fit_standalone_release()
515 			   0xffff0000 | (entry_point >> 16));  in fit_standalone_release()
517 			   ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffffa000);  in fit_standalone_release()
520 	writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);  in fit_standalone_release()
523 	/* writel(0x00050000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON02); */  in fit_standalone_release()
525 	return 0;  in fit_standalone_release()
541 		if (delay == 0) {  in qos_priority_init()
542 			printf("Fail to set domain. PMU2_PWR_GATE_STS0=0x%x\n",  in qos_priority_init()
549 	for (i = 0; i < 16; i++)  in qos_priority_init()
561 		if (delay == 0) {  in qos_priority_init()
562 			printf("Fail to get ack on domain. PMU2_BIU_IDLE_ACK_STS0=0x%x\n",  in qos_priority_init()
574 		if (delay == 0) {  in qos_priority_init()
575 			printf("Fail to set idle on domain. PMU2_BIT_IDLE_STS0=0x%x\n",  in qos_priority_init()
615 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG);  in arch_cpu_init()
619 	writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);  in arch_cpu_init()
628 	writel(0x0a100000, PERI_GRF_BASE + PERI_GRF_AUDIO_CON);  in arch_cpu_init()
631 	writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);  in arch_cpu_init()
636 	writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);  in arch_cpu_init()
644 	if (readl(GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L) == 0x2222) {  in arch_cpu_init()
646 			writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);  in arch_cpu_init()
647 			writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);  in arch_cpu_init()
648 			writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);  in arch_cpu_init()
650 			writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);  in arch_cpu_init()
651 			writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);  in arch_cpu_init()
652 			writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);  in arch_cpu_init()
659 	return 0;  in arch_cpu_init()