16 #define FIREWALL_DDR_BASE	0xff2e0000
17 #define FW_DDR_MST1_REG 	0x44
18 #define FW_DDR_MST6_REG 	0x58
19 #define FW_DDR_MST7_REG 	0x5c
20 #define FW_DDR_MST11_REG 	0x6c
21 #define FW_DDR_MST14_REG	0x78
22 #define FW_DDR_MST16_REG 	0x80
23 #define FW_DDR_MST_REG		0xf0
25 #define VENC_GRF_BASE		0xff320000
26 #define VENC_GRF_CON1		0x4
28 #define VPU_GRF_BASE		0xff340000
29 #define VPU_GRF_CON4		0x14
31 #define PMU_SGRF_BASE		0xff440000
32 #define PMU_SGRF_SOC_CON4	0x10
33 #define PMU_SGRF_SOC_CON5	0x14
34 #define PMU_SGRF_SOC_CON6	0x18
35 #define PMU_SGRF_SOC_CON8	0x20
36 #define PMU_SGRF_SOC_CON11	0x2c
38 #define PMU_CRU_BASE		0xff4b0000
39 #define PMU_CRU_GATE_CON00	0x800
40 #define PMU_CRU_SOFTRST_CON00	0xa00
42 #define GPIO1C_IOMUX_SEL_H	0x034
43 #define GPIO1D_IOMUX_SEL_L	0x038
44 #define GPIO1D_IOMUX_SEL_H	0x03c
46 #define CPU_PRIORITY_REG	0xff210008
54 		.virt = 0x0UL,
55 		.phys = 0x0UL,
56 		.size = 0xfc000000UL,
60 		.virt = 0xfc000000UL,
61 		.phys = 0xfc000000UL,
62 		.size = 0x04000000UL,
68 		0,
75 #define	GPIO0_IOC_BASE			0xFF540000
76 #define	GPIO1_IOC_BASE			0xFF560000
77 #define	GPIO2_IOC_BASE			0xFF570000
78 #define	GPIO3_IOC_BASE			0xFF560000
79 #define	GPIO4_IOC_BASE			0xFF550000
81 #define GPIO1_IOC_GPIO1D_IOMUX_SEL_L	(GPIO1_IOC_BASE + 0x38)
82 #define GPIO1_IOC_GPIO1C_DS_2		(GPIO1_IOC_BASE + 0x148)
83 #define GPIO1_IOC_GPIO1C_DS_3		(GPIO1_IOC_BASE + 0x14C)
84 #define GPIO1_IOC_GPIO1D_DS_0		(GPIO1_IOC_BASE + 0x150)
85 #define GPIO1_IOC_GPIO1D_DS_1		(GPIO1_IOC_BASE + 0x154)
86 #define GPIO1_IOC_GPIO1D_DS_2		(GPIO1_IOC_BASE + 0x158)
92 #define UART0_RX_M0_ADDR		(GPIO4_IOC_BASE + 0x94)
95 #define UART0_TX_M0_OFFSET		0
96 #define UART0_TX_M0_ADDR		(GPIO4_IOC_BASE + 0x98)
100 #define UART0_RX_M1_OFFSET		0
101 #define UART0_RX_M1_ADDR		(GPIO2_IOC_BASE + 0x40)
105 #define UART0_TX_M1_ADDR		(GPIO2_IOC_BASE + 0x40)
111 #define UART1_RX_M0_ADDR		(GPIO1_IOC_BASE + 0x84)
115 #define UART1_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x84)
120 #define UART1_RX_M1_ADDR		(GPIO4_IOC_BASE + 0x94)
124 #define UART1_TX_M1_ADDR		(GPIO4_IOC_BASE + 0x94)
129 #define UART2_RX_M0_OFFSET		0
130 #define UART2_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x60)
134 #define UART2_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x60)
138 #define UART2_RX_M1_OFFSET		0
139 #define UART2_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x28)
143 #define UART2_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x28)
148 #define UART3_RX_M0_OFFSET		0
149 #define UART3_RX_M0_ADDR		(GPIO4_IOC_BASE + 0x88)
153 #define UART3_TX_M0_ADDR		(GPIO4_IOC_BASE + 0x88)
158 #define UART3_RX_M1_ADDR		(GPIO4_IOC_BASE + 0x8C)
161 #define UART3_TX_M1_OFFSET		0
162 #define UART3_TX_M1_ADDR		(GPIO4_IOC_BASE + 0x90)
168 #define UART4_RX_M0_ADDR		(GPIO2_IOC_BASE + 0x40)
172 #define UART4_TX_M0_ADDR		(GPIO2_IOC_BASE + 0x40)
178 #define UART5_RX_M0_ADDR		(GPIO1_IOC_BASE + 0x20)
182 #define UART5_TX_M0_ADDR		(GPIO1_IOC_BASE + 0x20)
186 #define UART5_RX_M1_OFFSET		0
187 #define UART5_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x3c)
191 #define UART5_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x3c)
197 #define UART6_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x64)
201 #define UART6_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x64)
206 #define UART6_RX_M1_ADDR		(GPIO3_IOC_BASE + 0x70)
210 #define UART6_TX_M1_ADDR		(GPIO3_IOC_BASE + 0x70)
216 #define UART7_RX_M0_ADDR		(GPIO3_IOC_BASE + 0x68)
220 #define UART7_TX_M0_ADDR		(GPIO3_IOC_BASE + 0x68)
225 #define UART7_RX_M1_ADDR		(GPIO1_IOC_BASE + 0x28)
229 #define UART7_TX_M1_ADDR		(GPIO1_IOC_BASE + 0x28)
242 /* UART 0 */  in board_debug_uart_init()
243 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)  in board_debug_uart_init()
245 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
248 	set_uart_iomux_rx(0, 0);  in board_debug_uart_init()
249 	set_uart_iomux_tx(0, 0);  in board_debug_uart_init()
254 	set_uart_iomux_rx(0, 1);  in board_debug_uart_init()
255 	set_uart_iomux_tx(0, 1);  in board_debug_uart_init()
258 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)  in board_debug_uart_init()
260 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
263 	set_uart_iomux_rx(1, 0);  in board_debug_uart_init()
264 	set_uart_iomux_tx(1, 0);  in board_debug_uart_init()
273 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)  in board_debug_uart_init()
275 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
278 	set_uart_iomux_rx(2, 0);  in board_debug_uart_init()
279 	set_uart_iomux_tx(2, 0);  in board_debug_uart_init()
288 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)  in board_debug_uart_init()
290 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
293 	set_uart_iomux_rx(3, 0);  in board_debug_uart_init()
294 	set_uart_iomux_tx(3, 0);  in board_debug_uart_init()
303 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)  in board_debug_uart_init()
305 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
308 	set_uart_iomux_rx(4, 0);  in board_debug_uart_init()
309 	set_uart_iomux_tx(4, 0);  in board_debug_uart_init()
318 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)  in board_debug_uart_init()
320 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
323 	set_uart_iomux_rx(5, 0);  in board_debug_uart_init()
324 	set_uart_iomux_tx(5, 0);  in board_debug_uart_init()
333 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)  in board_debug_uart_init()
335 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
338 	set_uart_iomux_rx(6, 0);  in board_debug_uart_init()
339 	set_uart_iomux_tx(6, 0);  in board_debug_uart_init()
348 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)  in board_debug_uart_init()
350 	(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
353 	set_uart_iomux_rx(7, 0);  in board_debug_uart_init()
354 	set_uart_iomux_tx(7, 0);  in board_debug_uart_init()
369 	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);  in rockchip_stimer_init()
371 	if (reg & 0x1)  in rockchip_stimer_init()
374 	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));  in rockchip_stimer_init()
375 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);  in rockchip_stimer_init()
376 	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);  in rockchip_stimer_init()
378 	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);  in rockchip_stimer_init()
395 	writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);  in arch_cpu_init()
396 	writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);  in arch_cpu_init()
400 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);  in arch_cpu_init()
404 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);  in arch_cpu_init()
408 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);  in arch_cpu_init()
413 	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);  in arch_cpu_init()
423 	if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {  in arch_cpu_init()
429 	       writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);  in arch_cpu_init()
430 	       writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);  in arch_cpu_init()
431 	       writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);  in arch_cpu_init()
432 	       writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);  in arch_cpu_init()
433 	       writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);  in arch_cpu_init()
441 	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);  in arch_cpu_init()
445 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);  in arch_cpu_init()
448 	writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);  in arch_cpu_init()
449 	writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);  in arch_cpu_init()
450 	writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);  in arch_cpu_init()
455 	writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);  in arch_cpu_init()
458 	writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);  in arch_cpu_init()
459 	writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);  in arch_cpu_init()
460 	writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);  in arch_cpu_init()
464 	return 0;  in arch_cpu_init()
473 	writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);  in spl_fit_standalone_release()
476 	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);  in spl_fit_standalone_release()
477 	/* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */  in spl_fit_standalone_release()
479 	writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);  in spl_fit_standalone_release()
481 	writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);  in spl_fit_standalone_release()
483 	writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);  in spl_fit_standalone_release()
485 	writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);  in spl_fit_standalone_release()
487 	/* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */  in spl_fit_standalone_release()
489 	writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);  in spl_fit_standalone_release()
491 	return 0;  in spl_fit_standalone_release()