Lines Matching +full:0 +full:xff100000
17 #define CRU_BASE 0xFF440000
18 #define GRF_BASE 0xFF100000
19 #define UART2_BASE 0xFF130000
21 #define CRU_MISC_CON 0xff440084
22 #define FW_DDR_CON_REG 0xff7c0040
26 .virt = 0x0UL,
27 .phys = 0x0UL,
28 .size = 0xff000000UL,
32 .virt = 0xff000000UL,
33 .phys = 0xff000000UL,
34 .size = 0x1000000UL,
40 0,
59 rk_setreg(FW_DDR_CON_REG, 0x200); in arch_cpu_init()
69 return 0; in arch_cpu_init()
79 GPIO2A0_SEL_SHIFT = 0, in board_debug_uart_init()
88 IOMUX_SEL_UART2_SHIFT = 0, in board_debug_uart_init()
90 IOMUX_SEL_UART2_M0 = 0, in board_debug_uart_init()
95 writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); in board_debug_uart_init()
98 writel(0x83, &uart->lcr); in board_debug_uart_init()
99 writel(0x1, &uart->rbr); in board_debug_uart_init()
100 writel(0x3, &uart->lcr); in board_debug_uart_init()
114 writel(0x1, &uart->sfe); in board_debug_uart_init()