27 		.virt = 0x0UL,
28 		.phys = 0x0UL,
29 		.size = 0xff000000UL,
33 		.virt = 0xff000000UL,
34 		.phys = 0xff000000UL,
35 		.size = 0x01000000UL,
41 		0,
48 #define GRF_BASE	0xff000000
49 #define SGRF_BASE	0xff2b0000
50 #define CRU_BASE	0xff500000
55 	GPIO1C7_GPIO		= 0,
63 	GPIO1C6_GPIO		= 0,
71 	GPIO4D3_GPIO            = 0,
77 	GPIO4D2_GPIO            = 0,
83 	UART2_IO_SEL_M0		= 0,
89 	GPIO3B3_SEL_SRC_CTRL_IOMUX	= 0,
94 	GPIO3B3_SEL_PLUS_GPIO3_B3	= 0,
102 	GPIO3B2_SEL_SRC_CTRL_IOMUX	= 0,
105 	GPIO3B2_SEL_PLUS_SHIFT		= 0,
106 	GPIO3B2_SEL_PLUS_MASK		= GENMASK(2, 0),
107 	GPIO3B2_SEL_PLUS_GPIO3_B2	= 0,
117 	VCCIO3_SEL_BY_GPIO	= 0,
122 	VCCIO3_3V3		= 0,
148 	if (ret < 0) {  in rk_board_init()
150 		return 0;  in rk_board_init()
164 	return 0;  in rk_board_init()
167 #define SERVICE_CPU_BASE		0xff5c0000
168 #define SERVICE_VOICE_BASE		0xff5d0000
169 #define SERVICE_LOGIC_BASE		0xff5d8000
170 #define SERVICE_PERI_BASE		0xff5e0000
171 #define SERVICE_CPU_ADDR		(SERVICE_CPU_BASE + 0x80)
172 #define SERVICE_VOP_ADDR		(SERVICE_LOGIC_BASE + 0x100)
173 #define SERVICE_DMAC0_ADDR		(SERVICE_LOGIC_BASE + 0x0)
174 #define SERVICE_DMAC1_ADDR		(SERVICE_LOGIC_BASE + 0x80)
175 #define SERVICE_CRYPTO_ADDR		(SERVICE_LOGIC_BASE + 0x180)
176 #define SERVICE_VAD_ADDR		(SERVICE_VOICE_BASE + 0x80)
177 #define SERVICE_EMMC_ADDR		(SERVICE_PERI_BASE + 0x80)
178 #define SERVICE_GMAC_ADDR		(SERVICE_PERI_BASE + 0x100)
179 #define SERVICE_NAND_ADDR		(SERVICE_PERI_BASE + 0x180)
180 #define SERVICE_SDIO_ADDR		(SERVICE_PERI_BASE + 0x200)
181 #define SERVICE_SDMMC_ADDR		(SERVICE_PERI_BASE + 0x280)
182 #define SERVICE_SFC_ADDR		(SERVICE_PERI_BASE + 0x300)
183 #define SERVICE_USB_HOST_ADDR		(SERVICE_PERI_BASE + 0x380)
184 #define SERVICE_USB_OTG_ADDR		(SERVICE_PERI_BASE + 0x400)
186 #define DOS_PRIORITY_OFFSET		0x8
187 #define QOS_PRIORITY_P1_P0(p1, p0)	((((p1) & 0x3) << 8) |\
188 					(((p0) & 0x3) << 0))
193 	VCCIO4_3V3              = 0,
204 	rk_clrreg(&sgrf->con_secure0, 0x2b83);  in arch_cpu_init()
262 	return 0;  in arch_cpu_init()
284 	return 0;  in rk_board_init_f()
294 #if (CONFIG_DEBUG_UART_BASE == 0xFF0C0000)  in board_debug_uart_init()
301 #if (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)  in board_debug_uart_init()
322 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0E0000)  in board_debug_uart_init()
333 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0A0000)  in board_debug_uart_init()
344 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0B0000)  in board_debug_uart_init()
355 #elif (CONFIG_DEBUG_UART_BASE == 0xFF0D0000)  in board_debug_uart_init()
378 	if (cpu_node < 0) {  in fdt_fixup_cpu_idle()
388 		if (fdt_delprop((void *)blob, sub_node, "cpu-idle-states") < 0)  in fdt_fixup_cpu_idle()
392 	return 0;  in fdt_fixup_cpu_idle()
404 	if (opp_node < 0) {  in fdt_fixup_cpu_opp_table()
416 	if (cpu_node < 0) {  in fdt_fixup_cpu_opp_table()
426 		pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_cpu_opp_table()
429 	return 0;  in fdt_fixup_cpu_opp_table()
440 	if (opp_node < 0) {  in fdt_fixup_dmc_opp_table()
452 	if (dmc_node < 0) {  in fdt_fixup_dmc_opp_table()
459 		return 0;  in fdt_fixup_dmc_opp_table()
460 	pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_dmc_opp_table()
462 	return 0;  in fdt_fixup_dmc_opp_table()
474 	val = dss[0];  in fixup_pcfg_drive_strength()
477 		ds[0] = val;  in fixup_pcfg_drive_strength()
480 				"drive-strength", &val, 4) < 0)  in fixup_pcfg_drive_strength()
492 	for (i = 0; i < ARRAY_SIZE(path); i++) {  in fdt_fixup_pcfg()
494 		if (root_node < 0)  in fdt_fixup_pcfg()
507 	return 0;  in fdt_fixup_pcfg()
518 	if (thermal_node < 0) {  in fdt_fixup_thermal_zones()
530 			pp[0] = cpu_to_fdt32(val);  in fdt_fixup_thermal_zones()
533 	return 0;  in fdt_fixup_thermal_zones()
547 	return 0;  in rk_board_fdt_fixup()
554 	return 0;  in rk_board_early_fdt_fixup()