112 	int ret;  in configure_emmc()  local
121 	ret = dm_gpio_lookup_name("D9", &desc);  in configure_emmc()
122 	if (ret) {  in configure_emmc()
123 		debug("gpio ret=%d\n", ret);  in configure_emmc()
124 		return ret;  in configure_emmc()
126 	ret = dm_gpio_request(&desc, "emmc_pwren");  in configure_emmc()
127 	if (ret) {  in configure_emmc()
128 		debug("gpio_request ret=%d\n", ret);  in configure_emmc()
129 		return ret;  in configure_emmc()
131 	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);  in configure_emmc()
132 	if (ret) {  in configure_emmc()
133 		debug("gpio dir ret=%d\n", ret);  in configure_emmc()
134 		return ret;  in configure_emmc()
136 	ret = dm_gpio_set_value(&desc, 1);  in configure_emmc()
137 	if (ret) {  in configure_emmc()
138 		debug("gpio value ret=%d\n", ret);  in configure_emmc()
139 		return ret;  in configure_emmc()
148 	int ret = 0;  in rk_spl_board_init()  local
150 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);  in rk_spl_board_init()
151 	if (ret) {  in rk_spl_board_init()
157 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);  in rk_spl_board_init()
158 	if (ret) {  in rk_spl_board_init()
164 	ret = configure_emmc();  in rk_spl_board_init()
165 	if (ret) {  in rk_spl_board_init()
170 	return ret;  in rk_spl_board_init()
248 	int ret;  in veyron_init()  local
250 	ret = regulator_get_by_platname("vdd_arm", &dev);  in veyron_init()
251 	if (ret) {  in veyron_init()
253 		return ret;  in veyron_init()
257 	ret = regulator_set_value(dev, 1200000);  in veyron_init()
258 	if (ret)  in veyron_init()
259 		return ret;  in veyron_init()
261 	ret = regulator_set_value(dev, 1400000);  in veyron_init()
262 	if (ret)  in veyron_init()
263 		return ret;  in veyron_init()
266 	ret = rockchip_get_clk(&clk.dev);  in veyron_init()
267 	if (ret)  in veyron_init()
268 		return ret;  in veyron_init()
270 	ret = clk_set_rate(&clk, 1800000000);  in veyron_init()
271 	if (IS_ERR_VALUE(ret))  in veyron_init()
272 		return ret;  in veyron_init()
279 	int ret;  in rk_board_init()  local
283 		ret = veyron_init();  in rk_board_init()
284 		if (ret)  in rk_board_init()
285 			return ret;  in rk_board_init()
310 	int ret, i;  in do_clock()  local
313 	ret = rockchip_get_clk(&dev);  in do_clock()
314 	if (ret) {  in do_clock()
324 		ret = clk_request(dev, &clk);  in do_clock()
325 		if (ret < 0)  in do_clock()
349 	int ret;  in board_early_init_f()  local
356 	ret = rockchip_get_clk(&dev);  in board_early_init_f()
357 	if (ret) {  in board_early_init_f()
358 		debug("CLK init failed: %d\n", ret);  in board_early_init_f()
359 		return ret;  in board_early_init_f()
361 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);  in board_early_init_f()
362 	if (ret) {  in board_early_init_f()
364 		return ret;  in board_early_init_f()
368 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);  in board_early_init_f()
369 	if (ret) {  in board_early_init_f()
371 		return ret;  in board_early_init_f()