20 #define PMU_PWRDN_CON			0xff000018
21 #define GRF_CPU_CON1			0xff140504
23 #define USBPHY_GRF_BASE			0xff2c0000
24 #define VIDEO_PHY_BASE			0xff2e0000
25 #define FW_DDR_CON_REG			0xff534040
26 #define SERVICE_CORE_ADDR		0xff508000
27 #define QOS_PRIORITY			0x08
36 		.virt = 0x0UL,
37 		.phys = 0x0UL,
38 		.size = 0xff000000UL,
42 		.virt = 0xff000000UL,
43 		.phys = 0xff000000UL,
44 		.size = 0x01000000UL,
50 		0,
57 #define PMU_PWRDN_CON			0xff000018
58 #define GRF_BASE			0xff140000
59 #define CRU_BASE			0xff2b0000
60 #define VIDEO_PHY_BASE			0xff2e0000
61 #define SERVICE_CORE_ADDR		0xff508000
62 #define DDR_FW_BASE			0xff534000
64 #define FW_DDR_CON			0x40
66 #define QOS_PRIORITY			0x08
70 #define GRF_GPIO1A_DS2			0x0090
71 #define GRF_GPIO1B_DS2			0x0094
72 #define GRF_GPIO1A_E			0x00F0
73 #define GRF_GPIO1B_E			0x00F4
78 	GPIO1C1_MASK		= 0xf << GPIO1C1_SHIFT,
79 	GPIO1C1_GPIO		= 0,
82 	GPIO1C0_SHIFT		= 0,
83 	GPIO1C0_MASK		= 0xf << GPIO1C0_SHIFT,
84 	GPIO1C0_GPIO		= 0,
91 	GPIO1D3_MASK		= 0xf << GPIO1D3_SHIFT,
92 	GPIO1D3_GPIO		= 0,
97 	GPIO1D2_MASK		= 0xf << GPIO1D2_SHIFT,
98 	GPIO1D2_GPIO		= 0,
106 	GPIO1D7_MASK		= 0xf << GPIO1D7_SHIFT,
107 	GPIO1D7_GPIO		= 0,
111 	GPIO1D6_MASK		= 0xf << GPIO1D6_SHIFT,
112 	GPIO1D6_GPIO		= 0,
116 	GPIO1D5_MASK		= 0xf << GPIO1D5_SHIFT,
117 	GPIO1D5_GPIO		= 0,
120 	GPIO1D4_SHIFT		= 0,
121 	GPIO1D4_MASK		= 0xf << GPIO1D4_SHIFT,
122 	GPIO1D4_GPIO		= 0,
129 	GPIO2B6_MASK		= 0xf << GPIO2B6_SHIFT,
130 	GPIO2B6_GPIO		= 0,
134 	GPIO2B4_SHIFT		= 0,
135 	GPIO2B4_MASK		= 0xf << GPIO2B4_SHIFT,
136 	GPIO2B4_GPIO		= 0,
144 	GPIO3A2_MASK		= 0xf << GPIO3A2_SHIFT,
145 	GPIO3A2_GPIO		= 0,
149 	GPIO3A1_MASK		= 0xf << GPIO3A1_SHIFT,
150 	GPIO3A1_GPIO		= 0,
155 	IOVSEL6_CTRL_SHIFT	= 0,
156 	IOVSEL6_CTRL_MASK	= BIT(0),
157 	VCCIO6_SEL_BY_GPIO	= 0,
162 	VCCIO6_3V3		= 0,
175 #define GPIO0_BASE		0xff040000
176 #define GPIO_SWPORTA_DDR	0x4
177 #define GPIO_EXT_PORTA		0x50
196 	return 0;  in grf_vccio6_vsel_init()
204 	writel(0x0, FW_DDR_CON_REG);  in arch_cpu_init()
208 		writel(0xFFFF0000, GRF_BASE + GRF_GPIO1A_DS2);  in arch_cpu_init()
209 		writel(0xFFFFFFFF, GRF_BASE + GRF_GPIO1A_E);  in arch_cpu_init()
212 		writel(0x00060002, GRF_BASE + GRF_GPIO1B_DS2);  in arch_cpu_init()
213 		writel(0x003C0038, GRF_BASE + GRF_GPIO1B_E);  in arch_cpu_init()
224     (CONFIG_DEBUG_UART_BASE != 0xff160000) || \  in arch_cpu_init()
225     (CONFIG_DEBUG_UART_CHANNEL != 0)  in arch_cpu_init()
246 	writel(0x82, VIDEO_PHY_BASE + 0x0000);  in arch_cpu_init()
247 	writel(0x05, VIDEO_PHY_BASE + 0x03ac);  in arch_cpu_init()
256 		writel(0x04, USBPHY_GRF_BASE + 0x8000);  in arch_cpu_init()
257 		writel(0x46, USBPHY_GRF_BASE + 0x8004);  in arch_cpu_init()
258 		writel(0xdb, USBPHY_GRF_BASE + 0x8008);  in arch_cpu_init()
259 		writel(0x04, USBPHY_GRF_BASE + 0x8400);  in arch_cpu_init()
260 		writel(0x46, USBPHY_GRF_BASE + 0x8404);  in arch_cpu_init()
261 		writel(0xdb, USBPHY_GRF_BASE + 0x8408);  in arch_cpu_init()
264 	return 0;  in arch_cpu_init()
267 #define GRF_BASE		0xff140000
268 #define UART2_BASE		0xff160000
269 #define CRU_BASE		0xff2b0000
275 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)  in board_debug_uart_init()
279 		     UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);  in board_debug_uart_init()
288 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)  in board_debug_uart_init()
292 		     UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);  in board_debug_uart_init()
306 		CON_IOMUX_UART2SEL_M0	= 0,  in board_debug_uart_init()
314 		     UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);  in board_debug_uart_init()
362 	if (ret < 0) {  in set_armclk_rate()
368 	return 0;  in set_armclk_rate()
380 	if (opp_node < 0) {  in fdt_fixup_cpu_opp_table()
392 	if (cpu_node < 0) {  in fdt_fixup_cpu_opp_table()
402 		pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_cpu_opp_table()
405 	return 0;  in fdt_fixup_cpu_opp_table()
416 	if (opp_node < 0) {  in fdt_fixup_dmc_opp_table()
428 	if (dmc_node < 0) {  in fdt_fixup_dmc_opp_table()
435 		return 0;  in fdt_fixup_dmc_opp_table()
436 	pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_dmc_opp_table()
438 	return 0;  in fdt_fixup_dmc_opp_table()
449 	if (opp_node < 0) {  in fdt_fixup_gpu_opp_table()
461 	if (gpu_node < 0) {  in fdt_fixup_gpu_opp_table()
468 		return 0;  in fdt_fixup_gpu_opp_table()
469 	pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_gpu_opp_table()
471 	return 0;  in fdt_fixup_gpu_opp_table()
483 	val = dss[0];  in fixup_pcfg_drive_strength()
486 		ds[0] = val;  in fixup_pcfg_drive_strength()
489 				"drive-strength", &val, 4) < 0)  in fixup_pcfg_drive_strength()
501 	if (root_node < 0)  in fdt_fixup_pcfg()
514 	return 0;  in fdt_fixup_pcfg()
521 	do_fixup_by_path((void *)blob, path, "status", "disabled", sizeof("disabled"), 0);  in fdt_fixup_bus_apll()
523 	return 0;  in fdt_fixup_bus_apll()
534 	if (scmi_clk_node < 0) {  in fdt_fixup_cpu_gpu_clk()
541 		return 0;  in fdt_fixup_cpu_gpu_clk()
543 	cpu_node = fdt_path_offset(blob, "/cpus/cpu@0");  in fdt_fixup_cpu_gpu_clk()
544 	if (cpu_node < 0) {  in fdt_fixup_cpu_gpu_clk()
552 	 *	clocks = <&scmi_clk 0>;  in fdt_fixup_cpu_gpu_clk()
558 		return 0;  in fdt_fixup_cpu_gpu_clk()
560 		pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_cpu_gpu_clk()
561 		pp[1] = cpu_to_fdt32(0);  in fdt_fixup_cpu_gpu_clk()
565 	if (gpu_node < 0) {  in fdt_fixup_cpu_gpu_clk()
579 		return 0;  in fdt_fixup_cpu_gpu_clk()
581 		pp[0] = cpu_to_fdt32(phandle);  in fdt_fixup_cpu_gpu_clk()
584 	return 0;  in fdt_fixup_cpu_gpu_clk()
594 	if (node < 0) {  in fdt_fixup_i2s_soft_reset()
609 		return 0;  in fdt_fixup_i2s_soft_reset()
613 	return 0;  in fdt_fixup_i2s_soft_reset()
616 #define RKPM_SLP_ARMPD			BIT(0)
628 	if (suspend_node < 0) {  in fdt_fixup_rockchip_suspend()
636 		return 0;  in fdt_fixup_rockchip_suspend()
645 		printf("Failed to set rockchip,sleep-mode-config = 0x%x\n", mode);  in fdt_fixup_rockchip_suspend()
647 		debug("set rockchip,sleep-mode-config = 0x%x\n", mode);  in fdt_fixup_rockchip_suspend()
649 	return 0;  in fdt_fixup_rockchip_suspend()
670 	      fdt32_to_cpu(min[0]), fdt32_to_cpu(max[0]));  in fixup_regulators_px30s()
673 	if (*min == *max && fdt32_to_cpu(min[0]) == 1000000) {  in fixup_regulators_px30s()
676 		if (mem_node < 0)  in fixup_regulators_px30s()
687 		min[0] = cpu_to_fdt32(900000);  in fixup_regulators_px30s()
688 		max[0] = cpu_to_fdt32(900000);  in fixup_regulators_px30s()
697 		if (mem_node < 0)  in fixup_regulators_px30s()
727 		if (mem_node < 0)  in fixup_regulators_px30()
732 				"regulator-on-in-suspend", NULL, 0))  in fixup_regulators_px30()
745 	if (parent_node < 0)  in fixup_regulators()
765 	if (root_node < 0)  in fdt_fixup_regulator()
777 					return 0;  in fdt_fixup_regulator()
783 	return 0;  in fdt_fixup_regulator()
803 	return 0;  in rk_board_fdt_fixup()
810 	return 0;  in rk_board_early_fdt_fixup()
825 		run_command("rbrom", 0);  in do_board_download()
833 	u32 ret = 0;  in rk_board_init()
838 		return 0;  in rk_board_init()
841 	return 0;  in rk_board_init()