Lines Matching +full:0 +full:x504
18 #define SDRAM_CONFIG 0x3148400
19 #define SDRAM_MODE 0x62
20 #define SDRAM_CONTROL 0x4041000
21 #define SDRAM_TIME_CTRL_LOW 0x11602220
22 #define SDRAM_TIME_CTRL_HI 0x40c
23 #define SDRAM_OPEN_PAGE_EN 0x0
25 #define SDRAM_BANK0_SIZE 0x3ff0001
26 #define SDRAM_ADDR_CTRL 0x10
28 #define SDRAM_OP_NOP 0x05
29 #define SDRAM_OP_SETMODE 0x03
31 #define SDRAM_PAD_CTRL_WR_EN 0x80000000
32 #define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
33 #define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
34 #define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
40 #define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
41 #define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
47 #define MSAR_ARMDDRCLCK_MASK 0x000000f0
48 #define MSAR_ARMDDRCLCK_H_MASK 0x00000100
50 #define MSAR_ARMDDRCLCK_333_167 0x00000000
51 #define MSAR_ARMDDRCLCK_500_167 0x00000030
52 #define MSAR_ARMDDRCLCK_667_167 0x00000060
53 #define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
54 #define MSAR_ARMDDRCLCK_400_200 0x00000010
55 #define MSAR_ARMDDRCLCK_600_200 0x00000050
56 #define MSAR_ARMDDRCLCK_800_200 0x00000070
58 #define FTDLL_DDR1_166MHZ 0x0047F001
60 #define FTDLL_DDR1_200MHZ 0x0044D001
78 /* move internal registers from the default 0xD0000000
80 ldr r3, =0xD0000000
81 add r3, r3, #0x20000
82 str r4, [r3, #0x80]
85 add r3, r4, #0x01000
88 ldr r6, =0x00000001
89 str r6, [r3, #0x480]
92 add r3, r4, #0x31000
95 ldr r6, =0x00000030
96 str r6, [r3, #0xd00]
99 add r3, r4, #0x01000
101 /* set all dram windows to 0 */
102 mov r6, #0
103 str r6, [r3, #0x504]
104 str r6, [r3, #0x50C]
105 str r6, [r3, #0x514]
106 str r6, [r3, #0x51C]
110 str r6, [r3, #0x400]
114 str r6, [r3, #0x404]
118 str r6, [r3, #0x410]
120 /* 4) Write SDRAM bank 0 size register */
122 str r6, [r3, #0x504]
127 str r6, [r3, #0x414]
131 str r6, [r3, #0x408]
135 str r6, [r3, #0x40C]
147 str r6, [r3, #0x418]
151 ldr r6, [r3, #0x418]
152 cmp r6, #0
157 str r6, [r3, #0x41C]
161 str r6, [r3, #0x418]
165 ldr r6, [r3, #0x418]
166 cmp r6, #0
170 ldr r6, [r3, #0x4C0]
174 str r6, [r3, #0x4C0]
184 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
185 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
189 str r6, [r3, #0x4C0]
192 ldr r6, [r3, #0x4C4]
196 str r6, [r3, #0x4C4]
207 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
212 str r6, [r3, #0x4C4]
220 ldr r6, [r3, #0x4C0]
222 str r6, [r3, #0x4C0]
228 str r6, [r3, #0x4C0]
231 ldr r6, [r3, #0x4C4]
233 str r6, [r3, #0x4C4]
239 str r6, [r3, #0x4C4]
245 ldr r3, =0x10000
246 ldr r6, [r3, #0x010]
268 ldr r6, =0
272 add r3, r4, #0x01000
274 ldr r2, [r3, #0x484]
276 str r2, [r3, #0x484]
280 str r6, [r3, #0x500]
281 ldr r6, =0x7fff0001
282 str r6, [r3, #0x504]