107 		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)  in io_settings_ddr3()
112 		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)  in io_settings_ddr3()
133 	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &  in do_io_settings()
141 	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &  in do_io_settings()
148 	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &  in do_io_settings()
155 	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &  in do_io_settings()
162 	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &  in do_io_settings()
169 	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &  in do_io_settings()
177 	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &  in do_io_settings()
213 		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
222 		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);  in srcomp_enable()
228 				readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
233 			while (((readl((*ctrl)->control_srcomp_north_side + i*4)  in srcomp_enable()
239 				readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
245 		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);  in srcomp_enable()
254 				readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
260 				readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
267 			readl((*ctrl)->control_srcomp_east_side_wkup);  in srcomp_enable()
272 			readl((*ctrl)->control_srcomp_east_side_wkup);  in srcomp_enable()
276 		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);  in srcomp_enable()
280 		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);  in srcomp_enable()
285 			while (((readl((*ctrl)->control_srcomp_north_side + i*4)  in srcomp_enable()
291 				readl((*ctrl)->control_srcomp_north_side + i*4);  in srcomp_enable()
297 		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &  in srcomp_enable()
302 			readl((*ctrl)->control_srcomp_east_side_wkup);  in srcomp_enable()
348 	switch (readl(CONTROL_ID_CODE)) {  in init_omap_revision()
388 	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);  in omap_die_id()
389 	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);  in omap_die_id()
390 	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);  in omap_die_id()
391 	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);  in omap_die_id()
410 	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;  in warm_reset()
428 	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;  in setup_warmreset_time()
463 	value = readl((*ctrl)->control_pbias);  in vmmc_pbias_config()
480 	value = readl((*ctrl)->control_pbias);  in vmmc_pbias_config()