66 	unsigned int regval;  in do_emif4_init()  local
68 	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |  in do_emif4_init()
70 	writel(regval, &emif4_base->ddr_phyctrl1);  in do_emif4_init()
71 	writel(regval, &emif4_base->ddr_phyctrl1_shdw);  in do_emif4_init()
75 	regval = readl(&emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
76 	regval |= (1<<10);  in do_emif4_init()
77 	writel(regval, &emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
83 	regval |= (1<<0);  in do_emif4_init()
84 	writel(regval, &emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
86 	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |  in do_emif4_init()
90 	writel(regval, &emif4_base->sdram_time1);  in do_emif4_init()
91 	writel(regval, &emif4_base->sdram_time1_shdw);  in do_emif4_init()
93 	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |  in do_emif4_init()
96 	writel(regval, &emif4_base->sdram_time2);  in do_emif4_init()
97 	writel(regval, &emif4_base->sdram_time2_shdw);  in do_emif4_init()
99 	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);  in do_emif4_init()
100 	writel(regval, &emif4_base->sdram_time3);  in do_emif4_init()
101 	writel(regval, &emif4_base->sdram_time3_shdw);  in do_emif4_init()
104 	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |  in do_emif4_init()
106 	writel(regval, &emif4_base->sdram_pwr_mgmt);  in do_emif4_init()
107 	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);  in do_emif4_init()
110 	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);  in do_emif4_init()
111 	writel(regval, &emif4_base->sdram_refresh_ctrl);  in do_emif4_init()
112 	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);  in do_emif4_init()
115 	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |  in do_emif4_init()
121 	writel(regval, &emif4_base->sdram_config);  in do_emif4_init()