22 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;  variable
70 	writel(regval, &emif4_base->ddr_phyctrl1);  in do_emif4_init()
71 	writel(regval, &emif4_base->ddr_phyctrl1_shdw);  in do_emif4_init()
72 	writel(0, &emif4_base->ddr_phyctrl2);  in do_emif4_init()
75 	regval = readl(&emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
77 	writel(regval, &emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
79 	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0);  in do_emif4_init()
81 	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);  in do_emif4_init()
84 	writel(regval, &emif4_base->sdram_iodft_tlgc);  in do_emif4_init()
90 	writel(regval, &emif4_base->sdram_time1);  in do_emif4_init()
91 	writel(regval, &emif4_base->sdram_time1_shdw);  in do_emif4_init()
96 	writel(regval, &emif4_base->sdram_time2);  in do_emif4_init()
97 	writel(regval, &emif4_base->sdram_time2_shdw);  in do_emif4_init()
100 	writel(regval, &emif4_base->sdram_time3);  in do_emif4_init()
101 	writel(regval, &emif4_base->sdram_time3_shdw);  in do_emif4_init()
106 	writel(regval, &emif4_base->sdram_pwr_mgmt);  in do_emif4_init()
107 	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);  in do_emif4_init()
111 	writel(regval, &emif4_base->sdram_refresh_ctrl);  in do_emif4_init()
112 	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);  in do_emif4_init()
121 	writel(regval, &emif4_base->sdram_config);  in do_emif4_init()