Lines Matching +full:clk +full:- +full:mgr
9 * Richard Woodruff <r-woodruff2@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
25 * get_sys_clk_speed() - determine reference oscillator speed
36 val = readl(&prm_base->clksrc_ctrl); in get_osc_clk_speed()
44 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1; in get_osc_clk_speed()
47 writel(val, &prcm_base->clksel_wkup); in get_osc_clk_speed()
50 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; in get_osc_clk_speed()
51 writel(val, &prcm_base->iclken_wkup); in get_osc_clk_speed()
53 val = readl(&prcm_base->fclken_wkup) | EN_GPT1; in get_osc_clk_speed()
54 writel(val, &prcm_base->fclken_wkup); in get_osc_clk_speed()
56 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
57 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
62 start = 20 + readl(&s32k_base->s32k_cr); in get_osc_clk_speed()
65 while (readl(&s32k_base->s32k_cr) < start); in get_osc_clk_speed()
68 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
71 while (readl(&s32k_base->s32k_cr) < (start + 20)) ; in get_osc_clk_speed()
72 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
73 cdiff = cend - cstart; /* get elapsed ticks */ in get_osc_clk_speed()
92 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
136 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_34xx()
138 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_34xx()
147 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
149 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_34xx()
153 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
154 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
157 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
158 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
161 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_34xx()
162 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
165 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_34xx()
168 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
171 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
174 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
177 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_34xx()
180 clrsetbits_le32(&prcm_base->clksel_gfx, in dpll3_init_34xx()
182 /* RESET MGR */ in dpll3_init_34xx()
183 clrsetbits_le32(&prcm_base->clksel_wkup, in dpll3_init_34xx()
186 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_34xx()
187 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
189 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_34xx()
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, in dpll3_init_34xx()
201 p0 = readl(&prcm_base->clken_pll); in dpll3_init_34xx()
204 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
206 p1 = readl(&prcm_base->clksel1_pll); in dpll3_init_34xx()
208 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
210 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
212 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
216 p2 = readl(&prcm_base->clksel_core); in dpll3_init_34xx()
226 p3 = (u32)&prcm_base->idlest_ckgen; in dpll3_init_34xx()
241 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_34xx()
242 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_34xx()
250 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll4_init_34xx()
252 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll4_init_34xx()
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); in dpll4_init_34xx()
256 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); in dpll4_init_34xx()
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); in dpll4_init_34xx()
259 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); in dpll4_init_34xx()
261 clrsetbits_le32(&prcm_base->clksel_dss, in dpll4_init_34xx()
263 clrsetbits_le32(&prcm_base->clksel_dss, in dpll4_init_34xx()
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); in dpll4_init_34xx()
267 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
271 clrsetbits_le32(&prcm_base->clksel2_pll, in dpll4_init_34xx()
272 0x0007FF00, ptr->m << 8); in dpll4_init_34xx()
275 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_34xx()
278 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); in dpll4_init_34xx()
281 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_34xx()
282 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_34xx()
294 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_34xx()
295 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
297 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
298 /* set m (11-bit multiplier) */ in dpll5_init_34xx()
299 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_34xx()
300 /* set n (7-bit divider)*/ in dpll5_init_34xx()
301 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_34xx()
303 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); in dpll5_init_34xx()
305 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_34xx()
306 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
320 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, in mpu_init_34xx()
321 0x0000001F, ptr->m2); in mpu_init_34xx()
324 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, in mpu_init_34xx()
325 0x0007FF00, ptr->m << 8); in mpu_init_34xx()
328 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, in mpu_init_34xx()
329 0x0000007F, ptr->n); in mpu_init_34xx()
332 clrsetbits_le32(&prcm_base->clken_pll_mpu, in mpu_init_34xx()
333 0x000000F0, ptr->fsel << 4); in mpu_init_34xx()
346 clrsetbits_le32(&prcm_base->clken_pll_iva2, in iva_init_34xx()
348 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_34xx()
351 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, in iva_init_34xx()
352 0x0000001F, ptr->m2); in iva_init_34xx()
355 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, in iva_init_34xx()
356 0x0007FF00, ptr->m << 8); in iva_init_34xx()
359 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, in iva_init_34xx()
360 0x0000007F, ptr->n); in iva_init_34xx()
363 clrsetbits_le32(&prcm_base->clken_pll_iva2, in iva_init_34xx()
364 0x000000F0, ptr->fsel << 4); in iva_init_34xx()
367 clrsetbits_le32(&prcm_base->clken_pll_iva2, in iva_init_34xx()
370 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_34xx()
393 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_36xx()
395 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_36xx()
399 clrsetbits_le32(&prcm_base->clksel1_emu, in dpll3_init_36xx()
403 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_36xx()
404 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
407 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_36xx()
408 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
411 clrsetbits_le32(&prcm_base->clksel1_pll, in dpll3_init_36xx()
412 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
415 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_36xx()
418 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_36xx()
421 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_36xx()
424 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_36xx()
427 clrsetbits_le32(&prcm_base->clksel_core, in dpll3_init_36xx()
430 clrsetbits_le32(&prcm_base->clksel_gfx, in dpll3_init_36xx()
432 /* RESET MGR */ in dpll3_init_36xx()
433 clrsetbits_le32(&prcm_base->clksel_wkup, in dpll3_init_36xx()
436 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_36xx()
437 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
439 clrsetbits_le32(&prcm_base->clken_pll, in dpll3_init_36xx()
442 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, in dpll3_init_36xx()
451 p0 = readl(&prcm_base->clken_pll); in dpll3_init_36xx()
454 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
456 p1 = readl(&prcm_base->clksel1_pll); in dpll3_init_36xx()
458 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
460 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
462 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
466 p2 = readl(&prcm_base->clksel_core); in dpll3_init_36xx()
476 p3 = (u32)&prcm_base->idlest_ckgen; in dpll3_init_36xx()
493 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_36xx()
494 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_36xx()
497 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); in dpll4_init_36xx()
500 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); in dpll4_init_36xx()
503 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); in dpll4_init_36xx()
506 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); in dpll4_init_36xx()
509 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
512 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); in dpll4_init_36xx()
515 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_36xx()
518 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); in dpll4_init_36xx()
521 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_36xx()
522 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_36xx()
534 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_36xx()
535 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_36xx()
537 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_36xx()
538 /* set m (11-bit multiplier) */ in dpll5_init_36xx()
539 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_36xx()
540 /* set n (7-bit divider)*/ in dpll5_init_36xx()
541 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_36xx()
543 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_36xx()
544 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_36xx()
558 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); in mpu_init_36xx()
561 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); in mpu_init_36xx()
564 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); in mpu_init_36xx()
577 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); in iva_init_36xx()
578 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_36xx()
581 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); in iva_init_36xx()
584 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); in iva_init_36xx()
587 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); in iva_init_36xx()
590 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); in iva_init_36xx()
592 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_36xx()
596 * prcm_init() - inits clocks for PRCM as defined in clocks.h
614 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); in prcm_init()
619 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); in prcm_init()
623 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); in prcm_init()
642 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); in prcm_init()
646 clrsetbits_le32(&prcm_base->clken_pll_mpu, in prcm_init()
648 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
658 clrsetbits_le32(&prcm_base->clken_pll_mpu, in prcm_init()
660 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, in prcm_init()
676 clrsetbits_le32(&prcm_base->clken_pll_mpu, in prcm_init()
678 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
690 clrsetbits_le32(&prcm_base->clken_pll_mpu, in prcm_init()
692 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, in prcm_init()
697 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
698 setbits_le32(&prcm_base->clksel_wkup, 1); in prcm_init()
711 setbits_le32(&prcm_base->iclken_usbhost, 1); in ehci_clocks_enable()
716 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); in ehci_clocks_enable()
718 setbits_le32(&prcm_base->iclken3_core, 0x00000004); in ehci_clocks_enable()
720 setbits_le32(&prcm_base->fclken3_core, 0x00000004); in ehci_clocks_enable()
724 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
731 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ in per_clocks_enable()
732 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ in per_clocks_enable()
733 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ in per_clocks_enable()
736 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ in per_clocks_enable()
737 setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ in per_clocks_enable()
738 setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ in per_clocks_enable()
742 setbits_le32(&prcm_base->fclken1_core, 0x00002000); in per_clocks_enable()
743 setbits_le32(&prcm_base->iclken1_core, 0x00002000); in per_clocks_enable()
746 setbits_le32(&prcm_base->fclken1_core, 0x00004000); in per_clocks_enable()
747 setbits_le32(&prcm_base->iclken1_core, 0x00004000); in per_clocks_enable()
750 setbits_le32(&prcm_base->fclken_per, 0x00000800); in per_clocks_enable()
751 setbits_le32(&prcm_base->iclken_per, 0x00000800); in per_clocks_enable()
755 setbits_le32(&prcm_base->fclken_per, 0x00002000); in per_clocks_enable()
756 setbits_le32(&prcm_base->iclken_per, 0x00002000); in per_clocks_enable()
759 setbits_le32(&prcm_base->fclken_per, 0x00004000); in per_clocks_enable()
760 setbits_le32(&prcm_base->iclken_per, 0x00004000); in per_clocks_enable()
763 setbits_le32(&prcm_base->fclken_per, 0x00008000); in per_clocks_enable()
764 setbits_le32(&prcm_base->iclken_per, 0x00008000); in per_clocks_enable()
767 setbits_le32(&prcm_base->fclken_per, 0x00010000); in per_clocks_enable()
768 setbits_le32(&prcm_base->iclken_per, 0x00010000); in per_clocks_enable()
771 setbits_le32(&prcm_base->fclken_per, 0x00020000); in per_clocks_enable()
772 setbits_le32(&prcm_base->iclken_per, 0x00020000); in per_clocks_enable()
777 setbits_le32(&prcm_base->fclken1_core, 0x00038000); in per_clocks_enable()
778 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ in per_clocks_enable()
781 setbits_le32(&prcm_base->iclken_wkup, 0x00000004); in per_clocks_enable()
784 out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON); in per_clocks_enable()
786 out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON); in per_clocks_enable()
787 out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON); in per_clocks_enable()
788 out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON); in per_clocks_enable()
789 out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON); in per_clocks_enable()
790 out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON); in per_clocks_enable()
791 out_le32(&prcm_base->fclken_dss, FCK_DSS_ON); in per_clocks_enable()
792 out_le32(&prcm_base->iclken_dss, ICK_DSS_ON); in per_clocks_enable()
794 out_le32(&prcm_base->fclken_cam, FCK_CAM_ON); in per_clocks_enable()
795 out_le32(&prcm_base->iclken_cam, ICK_CAM_ON); in per_clocks_enable()