Lines Matching +full:0 +full:x0000001f
56 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
112 *sys_clkin_sel = 0; in get_sys_clkin_sel()
137 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
138 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_34xx()
142 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't in dpll3_init_34xx()
148 0x001F0000, (CORE_M3X2 + 1) << 16) ; in dpll3_init_34xx()
150 0x001F0000, CORE_M3X2 << 16); in dpll3_init_34xx()
154 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
158 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
162 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
165 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_34xx()
169 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()
172 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_34xx()
175 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
178 0x00000003, CORE_L3_DIV); in dpll3_init_34xx()
181 0x00000007, GFX_DIV); in dpll3_init_34xx()
184 0x00000006, WKUP_RSM << 1); in dpll3_init_34xx()
187 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
190 0x00000007, PLL_LOCK); in dpll3_init_34xx()
202 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
204 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
208 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
210 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
212 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
214 clrbits_le32(&p1, 0x00000040); in dpll3_init_34xx()
218 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()
220 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_34xx()
222 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
224 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); in dpll3_init_34xx()
241 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_34xx()
242 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_34xx()
245 * Errata 1.50 Workaround for OMAP3 ES1.0 only in dpll4_init_34xx()
251 0x1F000000, (PER_M6X2 + 1) << 24); in dpll4_init_34xx()
253 0x1F000000, PER_M6X2 << 24); in dpll4_init_34xx()
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); in dpll4_init_34xx()
256 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); in dpll4_init_34xx()
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); in dpll4_init_34xx()
259 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); in dpll4_init_34xx()
262 0x00001F00, (PER_M3X2 + 1) << 8); in dpll4_init_34xx()
264 0x00001F00, PER_M3X2 << 8); in dpll4_init_34xx()
265 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ in dpll4_init_34xx()
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); in dpll4_init_34xx()
267 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
272 0x0007FF00, ptr->m << 8); in dpll4_init_34xx()
274 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ in dpll4_init_34xx()
275 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_34xx()
278 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); in dpll4_init_34xx()
281 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_34xx()
294 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_34xx()
295 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
297 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
299 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_34xx()
301 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_34xx()
303 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); in dpll5_init_34xx()
305 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_34xx()
319 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ in mpu_init_34xx()
321 0x0000001F, ptr->m2); in mpu_init_34xx()
325 0x0007FF00, ptr->m << 8); in mpu_init_34xx()
327 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ in mpu_init_34xx()
329 0x0000007F, ptr->n); in mpu_init_34xx()
333 0x000000F0, ptr->fsel << 4); in mpu_init_34xx()
345 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_34xx()
347 0x00000007, PLL_STOP); in iva_init_34xx()
348 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_34xx()
350 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ in iva_init_34xx()
352 0x0000001F, ptr->m2); in iva_init_34xx()
356 0x0007FF00, ptr->m << 8); in iva_init_34xx()
358 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ in iva_init_34xx()
360 0x0000007F, ptr->n); in iva_init_34xx()
364 0x000000F0, ptr->fsel << 4); in iva_init_34xx()
366 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_34xx()
368 0x00000007, PLL_LOCK); in iva_init_34xx()
392 /* Select relock bypass: CM_CLKEN_PLL[0:2] */ in dpll3_init_36xx()
394 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_36xx()
395 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_36xx()
400 0x001F0000, CORE_M3X2 << 16); in dpll3_init_36xx()
404 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
408 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
412 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
415 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_36xx()
419 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()
422 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_36xx()
425 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
428 0x00000003, CORE_L3_DIV); in dpll3_init_36xx()
431 0x00000007, GFX_DIV_36X); in dpll3_init_36xx()
434 0x00000006, WKUP_RSM << 1); in dpll3_init_36xx()
437 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
440 0x00000007, PLL_LOCK); in dpll3_init_36xx()
452 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_36xx()
454 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
458 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
460 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
462 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
464 clrbits_le32(&p1, 0x00000040); in dpll3_init_36xx()
468 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()
470 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_36xx()
472 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
474 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); in dpll3_init_36xx()
493 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_36xx()
494 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_36xx()
497 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); in dpll4_init_36xx()
499 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ in dpll4_init_36xx()
500 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); in dpll4_init_36xx()
502 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ in dpll4_init_36xx()
503 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); in dpll4_init_36xx()
506 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); in dpll4_init_36xx()
508 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ in dpll4_init_36xx()
509 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
512 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); in dpll4_init_36xx()
514 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ in dpll4_init_36xx()
515 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_36xx()
518 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); in dpll4_init_36xx()
521 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_36xx()
534 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_36xx()
535 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_36xx()
537 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_36xx()
539 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_36xx()
541 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_36xx()
543 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_36xx()
557 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ in mpu_init_36xx()
558 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); in mpu_init_36xx()
561 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); in mpu_init_36xx()
563 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ in mpu_init_36xx()
564 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); in mpu_init_36xx()
576 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_36xx()
577 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); in iva_init_36xx()
578 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_36xx()
580 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ in iva_init_36xx()
581 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); in iva_init_36xx()
584 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); in iva_init_36xx()
586 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ in iva_init_36xx()
587 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); in iva_init_36xx()
589 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_36xx()
590 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); in iva_init_36xx()
601 u32 osc_clk = 0, sys_clkin_sel; in prcm_init()
602 u32 clk_index, sil_index = 0; in prcm_init()
614 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); in prcm_init()
619 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); in prcm_init()
623 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); in prcm_init()
642 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); in prcm_init()
647 0x00000007, PLL_LOW_POWER_BYPASS); in prcm_init()
648 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
651 dpll3_init_36xx(0, clk_index); in prcm_init()
652 dpll4_init_36xx(0, clk_index); in prcm_init()
653 dpll5_init_36xx(0, clk_index); in prcm_init()
654 iva_init_36xx(0, clk_index); in prcm_init()
655 mpu_init_36xx(0, clk_index); in prcm_init()
659 0x00000007, PLL_LOCK); in prcm_init()
677 0x00000007, PLL_LOW_POWER_BYPASS); in prcm_init()
678 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
691 0x00000007, PLL_LOCK); in prcm_init()
697 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
716 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); in ehci_clocks_enable()
718 setbits_le32(&prcm_base->iclken3_core, 0x00000004); in ehci_clocks_enable()
720 setbits_le32(&prcm_base->fclken3_core, 0x00000004); in ehci_clocks_enable()
731 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ in per_clocks_enable()
732 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ in per_clocks_enable()
733 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ in per_clocks_enable()
736 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ in per_clocks_enable()
737 setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ in per_clocks_enable()
738 setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ in per_clocks_enable()
742 setbits_le32(&prcm_base->fclken1_core, 0x00002000); in per_clocks_enable()
743 setbits_le32(&prcm_base->iclken1_core, 0x00002000); in per_clocks_enable()
746 setbits_le32(&prcm_base->fclken1_core, 0x00004000); in per_clocks_enable()
747 setbits_le32(&prcm_base->iclken1_core, 0x00004000); in per_clocks_enable()
750 setbits_le32(&prcm_base->fclken_per, 0x00000800); in per_clocks_enable()
751 setbits_le32(&prcm_base->iclken_per, 0x00000800); in per_clocks_enable()
755 setbits_le32(&prcm_base->fclken_per, 0x00002000); in per_clocks_enable()
756 setbits_le32(&prcm_base->iclken_per, 0x00002000); in per_clocks_enable()
759 setbits_le32(&prcm_base->fclken_per, 0x00004000); in per_clocks_enable()
760 setbits_le32(&prcm_base->iclken_per, 0x00004000); in per_clocks_enable()
763 setbits_le32(&prcm_base->fclken_per, 0x00008000); in per_clocks_enable()
764 setbits_le32(&prcm_base->iclken_per, 0x00008000); in per_clocks_enable()
767 setbits_le32(&prcm_base->fclken_per, 0x00010000); in per_clocks_enable()
768 setbits_le32(&prcm_base->iclken_per, 0x00010000); in per_clocks_enable()
771 setbits_le32(&prcm_base->fclken_per, 0x00020000); in per_clocks_enable()
772 setbits_le32(&prcm_base->iclken_per, 0x00020000); in per_clocks_enable()
777 setbits_le32(&prcm_base->fclken1_core, 0x00038000); in per_clocks_enable()
778 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ in per_clocks_enable()
781 setbits_le32(&prcm_base->iclken_wkup, 0x00000004); in per_clocks_enable()