25 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in set_lpmode_selfrefresh()  local
28 	reg = readl(&emif->emif_pwr_mgmt_ctrl);  in set_lpmode_selfrefresh()
32 	writel(reg, &emif->emif_pwr_mgmt_ctrl);  in set_lpmode_selfrefresh()
35 	readl(&emif->emif_pwr_mgmt_ctrl);  in set_lpmode_selfrefresh()
58 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in get_mr()  local
61 	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);  in get_mr()
63 		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);  in get_mr()
65 		mr = readl(&emif->emif_lpddr2_mode_reg_data);  in get_mr()
78 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in set_mr()  local
81 	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);  in set_mr()
82 	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);  in set_mr()
87 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in emif_reset_phy()  local
90 	iodft = readl(&emif->emif_iodft_tlgc);  in emif_reset_phy()
92 	writel(iodft, &emif->emif_iodft_tlgc);  in emif_reset_phy()
128 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in lpddr2_init()  local
131 	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);  in lpddr2_init()
137 	setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);  in lpddr2_init()
143 	writel(regs->sdram_config_init, &emif->emif_sdram_config);  in lpddr2_init()
144 	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);  in lpddr2_init()
152 	writel(regs->sdram_config, &emif->emif_sdram_config);  in lpddr2_init()
153 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);  in lpddr2_init()
156 	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);  in lpddr2_init()
166 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in emif_update_timings()  local
169 		writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);  in emif_update_timings()
171 		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);  in emif_update_timings()
173 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);  in emif_update_timings()
174 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);  in emif_update_timings()
175 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);  in emif_update_timings()
178 		writel(0, &emif->emif_pwr_mgmt_ctrl);  in emif_update_timings()
180 		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);  in emif_update_timings()
181 		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);  in emif_update_timings()
183 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);  in emif_update_timings()
184 	writel(regs->zq_config, &emif->emif_zq_config);  in emif_update_timings()
185 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);  in emif_update_timings()
186 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);  in emif_update_timings()
190 			&emif->emif_l3_config);  in emif_update_timings()
193 			&emif->emif_l3_config);  in emif_update_timings()
196 			&emif->emif_l3_config);  in emif_update_timings()
203 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in omap5_ddr3_leveling()  local
207 		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);  in omap5_ddr3_leveling()
219 	       &emif->emif_ddr_phy_ctrl_1);  in omap5_ddr3_leveling()
222 	       &emif->emif_ddr_phy_ctrl_1_shdw);  in omap5_ddr3_leveling()
226 	       & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);  in omap5_ddr3_leveling()
229 	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);  in omap5_ddr3_leveling()
232 	readl(&emif->emif_rd_wr_lvl_ctl);  in omap5_ddr3_leveling()
243 	       &emif->emif_rd_wr_lvl_ctl);  in omap5_ddr3_leveling()
248 	writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);  in omap5_ddr3_leveling()
254 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in update_hwleveling_output()  local
258 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];  in update_hwleveling_output()
259 	phy = readl(&emif->emif_ddr_phy_ctrl_1);  in update_hwleveling_output()
262 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;  in update_hwleveling_output()
271 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;  in update_hwleveling_output()
272 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];  in update_hwleveling_output()
281 	emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;  in update_hwleveling_output()
282 	emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];  in update_hwleveling_output()
291 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);  in update_hwleveling_output()
292 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);  in update_hwleveling_output()
293 	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);  in update_hwleveling_output()
298 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in dra7_ddr3_leveling()  local
301 	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,  in dra7_ddr3_leveling()
305 	clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,  in dra7_ddr3_leveling()
310 	clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,  in dra7_ddr3_leveling()
314 	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);  in dra7_ddr3_leveling()
319 	if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {  in dra7_ddr3_leveling()
325 	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);  in dra7_ddr3_leveling()
337 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in dra7_ddr3_init()  local
341 		writel(0x0, &emif->emif_pwr_mgmt_ctrl);  in dra7_ddr3_init()
346 	       &emif->emif_sdram_ref_ctrl);  in dra7_ddr3_init()
348 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);  in dra7_ddr3_init()
349 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);  in dra7_ddr3_init()
350 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);  in dra7_ddr3_init()
352 	writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);  in dra7_ddr3_init()
353 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);  in dra7_ddr3_init()
354 	writel(regs->zq_config, &emif->emif_zq_config);  in dra7_ddr3_init()
355 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);  in dra7_ddr3_init()
356 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);  in dra7_ddr3_init()
357 	writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);  in dra7_ddr3_init()
359 	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);  in dra7_ddr3_init()
360 	writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);  in dra7_ddr3_init()
362 	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);  in dra7_ddr3_init()
364 	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);  in dra7_ddr3_init()
365 	writel(regs->sdram_config_init, &emif->emif_sdram_config);  in dra7_ddr3_init()
369 	writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);  in dra7_ddr3_init()
377 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in omap5_ddr3_init()  local
379 	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);  in omap5_ddr3_init()
380 	writel(regs->sdram_config_init, &emif->emif_sdram_config);  in omap5_ddr3_init()
387 	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);  in omap5_ddr3_init()
390 	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);  in omap5_ddr3_init()
391 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);  in omap5_ddr3_init()
392 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);  in omap5_ddr3_init()
394 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);  in omap5_ddr3_init()
396 	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);  in omap5_ddr3_init()
397 	writel(regs->sdram_config_init, &emif->emif_sdram_config);  in omap5_ddr3_init()
400 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);  in omap5_ddr3_init()
1107 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in emif_get_device_details()  local
1115 		writel(phy, &emif->emif_ddr_phy_ctrl_1);  in emif_get_device_details()
1215 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;  in emif_post_init_config()  local
1224 		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);  in emif_post_init_config()
1425 	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;  in sdram_init()  local
1426 	u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);  in sdram_init()