Lines Matching +full:sense +full:- +full:freq
9 * SPDX-License-Identifier: GPL-2.0+
21 static int emif1_enabled = -1, emif2_enabled = -1;
28 reg = readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
32 writel(reg, &emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
35 readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()
61 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); in get_mr()
63 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); in get_mr()
65 mr = readl(&emif->emif_lpddr2_mode_reg_data); in get_mr()
81 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); in set_mr()
82 writel(mr_val, &emif->emif_lpddr2_mode_reg_data); in set_mr()
90 iodft = readl(&emif->emif_iodft_tlgc); in emif_reset_phy()
92 writel(iodft, &emif->emif_iodft_tlgc); in emif_reset_phy()
104 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); in do_lpddr2_init()
112 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); in do_lpddr2_init()
113 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); in do_lpddr2_init()
117 * Encoding of RL in MR2 is (RL - 2) in do_lpddr2_init()
120 set_mr(base, cs, mr_addr, mr_regs->mr2); in do_lpddr2_init()
122 if (mr_regs->mr3 > 0) in do_lpddr2_init()
123 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); in do_lpddr2_init()
131 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); in lpddr2_init()
134 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM in lpddr2_init()
137 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in lpddr2_init()
141 * un-locked frequency & default RL in lpddr2_init()
143 writel(regs->sdram_config_init, &emif->emif_sdram_config); in lpddr2_init()
144 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); in lpddr2_init()
149 if (regs->sdram_config & EMIF_REG_EBANK_MASK) in lpddr2_init()
152 writel(regs->sdram_config, &emif->emif_sdram_config); in lpddr2_init()
153 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); in lpddr2_init()
156 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in lpddr2_init()
169 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); in emif_update_timings()
171 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); in emif_update_timings()
173 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); in emif_update_timings()
174 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); in emif_update_timings()
175 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); in emif_update_timings()
178 writel(0, &emif->emif_pwr_mgmt_ctrl); in emif_update_timings()
180 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); in emif_update_timings()
181 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); in emif_update_timings()
183 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); in emif_update_timings()
184 writel(regs->zq_config, &emif->emif_zq_config); in emif_update_timings()
185 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); in emif_update_timings()
186 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); in emif_update_timings()
190 &emif->emif_l3_config); in emif_update_timings()
193 &emif->emif_l3_config); in emif_update_timings()
196 &emif->emif_l3_config); in emif_update_timings()
205 /* keep sdram in self-refresh */ in omap5_ddr3_leveling()
207 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); in omap5_ddr3_leveling()
211 * Set invert_clkout (if activated)--DDR_PHYCTRL_1 in omap5_ddr3_leveling()
218 writel(regs->emif_ddr_phy_ctlr_1, in omap5_ddr3_leveling()
219 &emif->emif_ddr_phy_ctrl_1); in omap5_ddr3_leveling()
221 writel(regs->emif_ddr_phy_ctlr_1, in omap5_ddr3_leveling()
222 &emif->emif_ddr_phy_ctrl_1_shdw); in omap5_ddr3_leveling()
226 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); in omap5_ddr3_leveling()
229 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); in omap5_ddr3_leveling()
232 readl(&emif->emif_rd_wr_lvl_ctl); in omap5_ddr3_leveling()
239 * Launch 8 incremental WR_LVL- to compensate for in omap5_ddr3_leveling()
243 &emif->emif_rd_wr_lvl_ctl); in omap5_ddr3_leveling()
248 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); in omap5_ddr3_leveling()
258 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; in update_hwleveling_output()
259 phy = readl(&emif->emif_ddr_phy_ctrl_1); in update_hwleveling_output()
262 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; in update_hwleveling_output()
271 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; in update_hwleveling_output()
272 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; in update_hwleveling_output()
281 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; in update_hwleveling_output()
282 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; in update_hwleveling_output()
291 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); in update_hwleveling_output()
292 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); in update_hwleveling_output()
293 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); in update_hwleveling_output()
301 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, in dra7_ddr3_leveling()
305 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, in dra7_ddr3_leveling()
310 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, in dra7_ddr3_leveling()
314 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); in dra7_ddr3_leveling()
319 if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { in dra7_ddr3_leveling()
325 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in dra7_ddr3_leveling()
341 writel(0x0, &emif->emif_pwr_mgmt_ctrl); in dra7_ddr3_init()
345 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, in dra7_ddr3_init()
346 &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
348 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in dra7_ddr3_init()
349 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); in dra7_ddr3_init()
350 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); in dra7_ddr3_init()
352 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); in dra7_ddr3_init()
353 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); in dra7_ddr3_init()
354 writel(regs->zq_config, &emif->emif_zq_config); in dra7_ddr3_init()
355 writel(regs->temp_alert_config, &emif->emif_temp_alert_config); in dra7_ddr3_init()
356 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); in dra7_ddr3_init()
357 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); in dra7_ddr3_init()
359 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); in dra7_ddr3_init()
360 writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); in dra7_ddr3_init()
362 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
364 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); in dra7_ddr3_init()
365 writel(regs->sdram_config_init, &emif->emif_sdram_config); in dra7_ddr3_init()
369 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
371 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) in dra7_ddr3_init()
379 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in omap5_ddr3_init()
380 writel(regs->sdram_config_init, &emif->emif_sdram_config); in omap5_ddr3_init()
387 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); in omap5_ddr3_init()
390 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in omap5_ddr3_init()
391 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); in omap5_ddr3_init()
392 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); in omap5_ddr3_init()
394 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); in omap5_ddr3_init()
396 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); in omap5_ddr3_init()
397 writel(regs->sdram_config_init, &emif->emif_sdram_config); in omap5_ddr3_init()
400 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); in omap5_ddr3_init()
414 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
418 * types and densities. Derived from JESD209-2 section 2.4
451 static void set_ddr_clk_period(u32 freq) in set_ddr_clk_period() argument
454 * period = 1/freq in set_ddr_clk_period()
455 * period_in_ns = 10^9/freq in set_ddr_clk_period()
458 *T_den = freq; in set_ddr_clk_period()
468 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); in ns_2_cycles()
478 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); in ns_x2_2_cycles()
489 return -1; in addressing_table_index()
516 u32 freq) in get_timings_table() argument
521 emif_assert(freq <= MAX_LPDDR2_FREQ); in get_timings_table()
525 * Start with the maximum allowed frequency - that is always safe in get_timings_table()
530 * i. Above or equal to the DDR frequency - safe in get_timings_table()
531 * ii. The lowest that satisfies condition (i) - optimal in get_timings_table()
534 temp = device_timings[i]->max_freq; in get_timings_table()
535 if ((temp >= freq) && (temp <= freq_nearest)) { in get_timings_table()
559 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; in get_sdram_config_reg()
563 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; in get_sdram_config_reg()
567 config_reg |= addressing->row_sz[cs0_device->io_width] << in get_sdram_config_reg()
570 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; in get_sdram_config_reg()
575 config_reg |= addressing->col_sz[cs0_device->io_width] << in get_sdram_config_reg()
581 static u32 get_sdram_ref_ctrl(u32 freq, in get_sdram_ref_ctrl() argument
585 freq_khz = freq / 1000; in get_sdram_ref_ctrl()
587 * refresh rate to be set is 'tREFI * freq in MHz in get_sdram_ref_ctrl()
590 val = addressing->t_REFI_us_x10 * freq_khz / 10000; in get_sdram_ref_ctrl()
601 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; in get_sdram_tim_1_reg()
604 if (addressing->num_banks == BANKS8) in get_sdram_tim_1_reg()
605 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / in get_sdram_tim_1_reg()
606 (4 * (*T_num)) - 1; in get_sdram_tim_1_reg()
608 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; in get_sdram_tim_1_reg()
612 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; in get_sdram_tim_1_reg()
615 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; in get_sdram_tim_1_reg()
618 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; in get_sdram_tim_1_reg()
621 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; in get_sdram_tim_1_reg()
624 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; in get_sdram_tim_1_reg()
634 val = max(min_tck->tCKE, timings->tCKE) - 1; in get_sdram_tim_2_reg()
637 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; in get_sdram_tim_2_reg()
644 val = ns_2_cycles(timings->tXSR) - 1; in get_sdram_tim_2_reg()
648 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; in get_sdram_tim_2_reg()
659 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); in get_sdram_tim_3_reg()
662 val = ns_2_cycles(timings->tRFCab) - 1; in get_sdram_tim_3_reg()
665 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; in get_sdram_tim_3_reg()
668 val = ns_2_cycles(timings->tZQCS) - 1; in get_sdram_tim_3_reg()
671 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; in get_sdram_tim_3_reg()
685 addressing->t_REFI_us_x10; in get_zq_config_reg()
689 addressing->t_REFI_us_x10; in get_zq_config_reg()
692 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; in get_zq_config_reg()
694 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; in get_zq_config_reg()
721 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; in get_temp_alert_config()
743 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; in get_read_idle_ctrl_reg()
745 /*Maximum value in normal conditions - suggested by hw team */ in get_read_idle_ctrl_reg()
754 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) in get_ddr_phy_ctrl_1() argument
760 if (freq <= 100000000) in get_ddr_phy_ctrl_1()
762 else if (freq <= 200000000) in get_ddr_phy_ctrl_1()
790 temp = dev_details.cs0_device_details->density; in get_emif_mem_size()
795 temp = dev_details.cs1_device_details->density; in get_emif_mem_size()
807 * 0x0: 16-MiB section in get_dmm_section_size_map()
808 * 0x1: 32-MiB section in get_dmm_section_size_map()
809 * 0x2: 64-MiB section in get_dmm_section_size_map()
810 * 0x3: 128-MiB section in get_dmm_section_size_map()
811 * 0x4: 256-MiB section in get_dmm_section_size_map()
812 * 0x5: 512-MiB section in get_dmm_section_size_map()
813 * 0x6: 1-GiB section in get_dmm_section_size_map()
814 * 0x7: 2-GiB section in get_dmm_section_size_map()
822 u32 freq, struct emif_regs *regs) in emif_calculate_regs() argument
829 emif_dev_details->cs0_device_details; in emif_calculate_regs()
831 emif_dev_details->cs1_device_details; in emif_calculate_regs()
833 emif_dev_details->cs0_device_timings; in emif_calculate_regs()
840 * make sense in emif_calculate_regs()
843 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); in emif_calculate_regs()
849 (cs1_dev_details->type == LPDDR2_TYPE_NVM) || in emif_calculate_regs()
850 (cs0_dev_details->type == cs1_dev_details->type)); in emif_calculate_regs()
851 emif_assert(freq <= MAX_LPDDR2_FREQ); in emif_calculate_regs()
853 set_ddr_clk_period(freq); in emif_calculate_regs()
861 timings = get_timings_table(cs0_dev_timings->ac_timings, freq); in emif_calculate_regs()
863 min_tck = cs0_dev_timings->min_tck; in emif_calculate_regs()
865 temp = addressing_table_index(cs0_dev_details->type, in emif_calculate_regs()
866 cs0_dev_details->density, in emif_calculate_regs()
867 cs0_dev_details->io_width); in emif_calculate_regs()
875 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, in emif_calculate_regs()
879 regs->sdram_config = get_sdram_config_reg(cs0_dev_details, in emif_calculate_regs()
883 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); in emif_calculate_regs()
885 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); in emif_calculate_regs()
887 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); in emif_calculate_regs()
889 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); in emif_calculate_regs()
891 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); in emif_calculate_regs()
893 regs->temp_alert_config = in emif_calculate_regs()
896 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, in emif_calculate_regs()
899 regs->emif_ddr_phy_ctlr_1_init = in emif_calculate_regs()
902 regs->emif_ddr_phy_ctlr_1 = in emif_calculate_regs()
903 get_ddr_phy_ctrl_1(freq, RL_FINAL); in emif_calculate_regs()
905 regs->freq = freq; in emif_calculate_regs()
907 print_timing_reg(regs->sdram_config_init); in emif_calculate_regs()
908 print_timing_reg(regs->sdram_config); in emif_calculate_regs()
909 print_timing_reg(regs->ref_ctrl); in emif_calculate_regs()
910 print_timing_reg(regs->sdram_tim1); in emif_calculate_regs()
911 print_timing_reg(regs->sdram_tim2); in emif_calculate_regs()
912 print_timing_reg(regs->sdram_tim3); in emif_calculate_regs()
913 print_timing_reg(regs->read_idle_ctrl); in emif_calculate_regs()
914 print_timing_reg(regs->temp_alert_config); in emif_calculate_regs()
915 print_timing_reg(regs->zq_config); in emif_calculate_regs()
916 print_timing_reg(regs->emif_ddr_phy_ctlr_1); in emif_calculate_regs()
917 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); in emif_calculate_regs()
926 return "LPDDR2-S4"; in get_lpddr2_type()
928 return "LPDDR2-S2"; in get_lpddr2_type()
1001 mfg_str = get_lpddr2_manufacturer(device->manufacturer); in display_sdram_details()
1002 type_str = get_lpddr2_type(device->type); in display_sdram_details()
1004 density = lpddr2_density_2_size_in_mbytes[device->density]; in display_sdram_details()
1033 /* DNV supported - But DNV is only supported for NVM */ in is_lpddr2_sdram_present()
1053 lpddr2_device->manufacturer = mr; in is_lpddr2_sdram_present()
1078 lpddr2_device->type = temp; in is_lpddr2_sdram_present()
1085 lpddr2_device->density = temp; in is_lpddr2_sdram_present()
1092 lpddr2_device->io_width = temp; in is_lpddr2_sdram_present()
1096 * have a device on this chip-select in is_lpddr2_sdram_present()
1115 writel(phy, &emif->emif_ddr_phy_ctrl_1); in emif_get_device_details()
1153 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set in do_sdram_init()
1154 * - Obtained from user otherwise in do_sdram_init()
1172 * - Default timings specified by JESD209-2 if in do_sdram_init()
1174 * - Obtained from user otherwise in do_sdram_init()
1190 if (emif_sdram_type(regs->sdram_config) == in do_sdram_init()
1199 if (warm_reset() && (emif_sdram_type(regs->sdram_config) == in do_sdram_init()
1224 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); in emif_post_init_config()
1260 emif1_size -= mapped_size; in dmm_init()
1261 emif2_size -= mapped_size; in dmm_init()
1263 section_cnt--; in dmm_init()
1268 * section- either EMIF1 or EMIF2 or none, but not both) in dmm_init()
1279 section_cnt--; in dmm_init()
1289 section_cnt--; in dmm_init()
1293 /* Only 1 section - either symmetric or single EMIF */ in dmm_init()
1298 /* 2 sections - 1 symmetric, 1 single EMIF */ in dmm_init()
1314 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); in dmm_init()
1315 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); in dmm_init()
1316 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); in dmm_init()
1317 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); in dmm_init()
1319 writel(lisa_map_regs->dmm_lisa_map_3, in dmm_init()
1320 &hw_lisa_map_regs->dmm_lisa_map_3); in dmm_init()
1321 writel(lisa_map_regs->dmm_lisa_map_2, in dmm_init()
1322 &hw_lisa_map_regs->dmm_lisa_map_2); in dmm_init()
1323 writel(lisa_map_regs->dmm_lisa_map_1, in dmm_init()
1324 &hw_lisa_map_regs->dmm_lisa_map_1); in dmm_init()
1325 writel(lisa_map_regs->dmm_lisa_map_0, in dmm_init()
1326 &hw_lisa_map_regs->dmm_lisa_map_0); in dmm_init()
1328 if (lisa_map_regs->is_ma_present) { in dmm_init()
1332 writel(lisa_map_regs->dmm_lisa_map_3, in dmm_init()
1333 &hw_lisa_map_regs->dmm_lisa_map_3); in dmm_init()
1334 writel(lisa_map_regs->dmm_lisa_map_2, in dmm_init()
1335 &hw_lisa_map_regs->dmm_lisa_map_2); in dmm_init()
1336 writel(lisa_map_regs->dmm_lisa_map_1, in dmm_init()
1337 &hw_lisa_map_regs->dmm_lisa_map_1); in dmm_init()
1338 writel(lisa_map_regs->dmm_lisa_map_0, in dmm_init()
1339 &hw_lisa_map_regs->dmm_lisa_map_0); in dmm_init()
1375 u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; in do_bug0039_workaround()
1376 u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; in do_bug0039_workaround()
1384 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1385 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1390 bug_00339_regs[i].read_reg - 1); in do_bug0039_workaround()
1393 ((bug_00339_regs[i].write_reg - 1) << 1)); in do_bug0039_workaround()
1396 (bug_00339_regs[i].write_reg << 1) - 1); in do_bug0039_workaround()
1400 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); in do_bug0039_workaround()
1402 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); in do_bug0039_workaround()
1415 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1417 * Doing (1) and (2) makes sense - first time initialization
1418 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1419 * Doing (1) and not (2) doen't make sense
1426 u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); in sdram_init()
1438 bypass_dpll((*prcm)->cm_clkmode_dpll_core); in sdram_init()
1440 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); in sdram_init()