59 		ind = (readl((*prcm)->cm_sys_clksel) &  in __get_sys_clk_index()
328 			(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);  in configure_mpu_dpll()
329 		bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);  in configure_mpu_dpll()
330 		clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,  in configure_mpu_dpll()
332 		setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,  in configure_mpu_dpll()
340 	do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");  in configure_mpu_dpll()
365 	clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,  in setup_usb_dpll()
370 	do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");  in setup_usb_dpll()
391 		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,  in setup_dplls()
394 		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,  in setup_dplls()
400 	writel(temp, (*prcm)->cm_clksel_core);  in setup_dplls()
405 	do_setup_dpll((*prcm)->cm_clkmode_dpll_per,  in setup_dplls()
417 	do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,  in setup_dplls()
422 	do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,  in setup_dplls()
603 		  (*prcm)->prm_abbldo_mpu_setup,  in scale_vcores()
604 		  (*prcm)->prm_abbldo_mpu_ctrl,  in scale_vcores()
605 		  (*prcm)->prm_irqstatus_mpu_2,  in scale_vcores()
616 		  (*prcm)->prm_abbldo_mm_setup,  in scale_vcores()
617 		  (*prcm)->prm_abbldo_mm_ctrl,  in scale_vcores()
618 		  (*prcm)->prm_irqstatus_mpu,  in scale_vcores()
629 		  (*prcm)->prm_abbldo_gpu_setup,  in scale_vcores()
630 		  (*prcm)->prm_abbldo_gpu_ctrl,  in scale_vcores()
631 		  (*prcm)->prm_irqstatus_mpu,  in scale_vcores()
642 		  (*prcm)->prm_abbldo_eve_setup,  in scale_vcores()
643 		  (*prcm)->prm_abbldo_eve_ctrl,  in scale_vcores()
644 		  (*prcm)->prm_irqstatus_mpu,  in scale_vcores()
655 		  (*prcm)->prm_abbldo_iva_setup,  in scale_vcores()
656 		  (*prcm)->prm_abbldo_iva_ctrl,  in scale_vcores()
657 		  (*prcm)->prm_irqstatus_mpu,  in scale_vcores()
742 	enable_clock_domain((*prcm)->cm_memif_clkstctrl,  in freq_update_core()
744 	wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);  in freq_update_core()
745 	wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);  in freq_update_core()
757 	writel(freq_config1, (*prcm)->cm_shadow_freq_config1);  in freq_update_core()
759 			(u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {  in freq_update_core()
771 		enable_clock_domain((*prcm)->cm_memif_clkstctrl,  in freq_update_core()
773 		wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);  in freq_update_core()
774 		wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);  in freq_update_core()
793 	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,  in setup_clocks_for_console()
798 	clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,  in setup_clocks_for_console()
803 	clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,  in setup_clocks_for_console()
808 	clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,  in setup_clocks_for_console()
813 	clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,  in setup_clocks_for_console()
818 	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,  in setup_clocks_for_console()