58 		/* SYS_CLKSEL - 1 to match the dpll param array indices */  in __get_sys_clk_index()
117 		printf("Bypassing DPLL failed %x\n", base);  in wait_for_bypass()
136 		printf("DPLL locking failed for %x\n", base);  in wait_for_lock()
212 				u8 lock, char *dpll)  in do_setup_dpll()  argument
224 		 * The Dpll has already been locked by rom code using CH.  in do_setup_dpll()
231 			debug("\n %s Dpll locked, but not for ideal M = %d,"  in do_setup_dpll()
233 				"N= %d" , dpll, params->m, params->n,  in do_setup_dpll()
236 			/* Dpll locked with ideal values for nominal opps. */  in do_setup_dpll()
237 			debug("\n %s Dpll already locked with ideal"  in do_setup_dpll()
238 						"nominal opp values", dpll);  in do_setup_dpll()
263 	/* Wait till the DPLL locks */  in do_setup_dpll()
280 	/* Find Core DPLL locked frequency first */  in omap_ddr_clk()
306  * Lock MPU dpll
341 	debug("MPU DPLL locked\n");  in configure_mpu_dpll()
354 	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction  in setup_usb_dpll()
369 	/* Now setup the dpll with the regular function */  in setup_usb_dpll()
382 	/* CORE dpll */  in setup_dplls()
385 	 * Do not lock the core DPLL now. Just set it up.  in setup_dplls()
386 	 * Core DPLL will be locked after setting up EMIF  in setup_dplls()
401 	debug("Core DPLL configured\n");  in setup_dplls()
403 	/* lock PER dpll */  in setup_dplls()
407 	debug("PER DPLL locked\n");  in setup_dplls()
409 	/* MPU dpll */  in setup_dplls()