Lines Matching refs:writel
44 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in get_mr()
59 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg); in set_mr()
60 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data); in set_mr()
84 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); in config_sdram_emif4d5()
85 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); in config_sdram_emif4d5()
86 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram_emif4d5()
88 writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config); in config_sdram_emif4d5()
89 writel(regs->emif_rd_wr_lvl_rmp_win, in config_sdram_emif4d5()
91 writel(regs->emif_rd_wr_lvl_rmp_ctl, in config_sdram_emif4d5()
93 writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl); in config_sdram_emif4d5()
94 writel(regs->emif_rd_wr_exec_thresh, in config_sdram_emif4d5()
103 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map); in config_sdram_emif4d5()
104 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map); in config_sdram_emif4d5()
105 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map); in config_sdram_emif4d5()
106 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config); in config_sdram_emif4d5()
114 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
115 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
116 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in config_sdram_emif4d5()
121 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram_emif4d5()
122 writel(regs->sdram_config, &cstat->secure_emif_sdram_config); in config_sdram_emif4d5()
127 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram_emif4d5()
128 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram_emif4d5()
132 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | in config_sdram_emif4d5()
134 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | in config_sdram_emif4d5()
137 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); in config_sdram_emif4d5()
140 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); in config_sdram_emif4d5()
167 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
168 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); in config_sdram()
169 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); in config_sdram()
170 writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ in config_sdram()
171 writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ in config_sdram()
172 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
175 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); in config_sdram()
176 writel(regs->sdram_config, &cstat->secure_emif_sdram_config); in config_sdram()
177 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
180 writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
185 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
186 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
188 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
189 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
190 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); in config_sdram()
194 writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); in config_sdram()
203 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); in set_sdram_timings()
204 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); in set_sdram_timings()
205 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); in set_sdram_timings()
206 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); in set_sdram_timings()
207 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); in set_sdram_timings()
208 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); in set_sdram_timings()
228 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); in ext_phy_settings_swlvl()
230 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); in ext_phy_settings_swlvl()
244 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); in ext_phy_settings_swlvl()
246 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); in ext_phy_settings_swlvl()
260 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); in ext_phy_settings_hwlvl()
261 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); in ext_phy_settings_hwlvl()
262 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); in ext_phy_settings_hwlvl()
263 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); in ext_phy_settings_hwlvl()
264 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23); in ext_phy_settings_hwlvl()
265 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw); in ext_phy_settings_hwlvl()
266 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24); in ext_phy_settings_hwlvl()
267 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw); in ext_phy_settings_hwlvl()
268 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25); in ext_phy_settings_hwlvl()
269 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw); in ext_phy_settings_hwlvl()
270 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26); in ext_phy_settings_hwlvl()
271 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw); in ext_phy_settings_hwlvl()
272 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27); in ext_phy_settings_hwlvl()
273 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw); in ext_phy_settings_hwlvl()
274 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28); in ext_phy_settings_hwlvl()
275 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw); in ext_phy_settings_hwlvl()
276 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29); in ext_phy_settings_hwlvl()
277 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw); in ext_phy_settings_hwlvl()
278 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30); in ext_phy_settings_hwlvl()
279 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw); in ext_phy_settings_hwlvl()
280 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31); in ext_phy_settings_hwlvl()
281 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw); in ext_phy_settings_hwlvl()
282 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32); in ext_phy_settings_hwlvl()
283 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw); in ext_phy_settings_hwlvl()
284 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33); in ext_phy_settings_hwlvl()
285 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw); in ext_phy_settings_hwlvl()
286 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34); in ext_phy_settings_hwlvl()
287 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); in ext_phy_settings_hwlvl()
288 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); in ext_phy_settings_hwlvl()
289 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); in ext_phy_settings_hwlvl()
290 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); in ext_phy_settings_hwlvl()
291 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); in ext_phy_settings_hwlvl()
297 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
298 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
299 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc); in ext_phy_settings_hwlvl()
314 writel(EMIF_REG_INITREF_DIS_MASK | 0x3100, in config_ddr_phy()
317 writel(regs->emif_ddr_phy_ctlr_1, in config_ddr_phy()
319 writel(regs->emif_ddr_phy_ctlr_1, in config_ddr_phy()
338 writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); in config_cmd_ctrl()
339 writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); in config_cmd_ctrl()
341 writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); in config_cmd_ctrl()
342 writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); in config_cmd_ctrl()
344 writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); in config_cmd_ctrl()
345 writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); in config_cmd_ctrl()
359 writel(data->datardsratio0, in config_ddr_data()
361 writel(data->datawdsratio0, in config_ddr_data()
363 writel(data->datawiratio0, in config_ddr_data()
365 writel(data->datagiratio0, in config_ddr_data()
367 writel(data->datafwsratio0, in config_ddr_data()
369 writel(data->datawrsratio0, in config_ddr_data()
379 writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl); in config_io_ctrl()
380 writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl); in config_io_ctrl()
381 writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl); in config_io_ctrl()
382 writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl); in config_io_ctrl()
383 writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl); in config_io_ctrl()
385 writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl); in config_io_ctrl()
386 writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl); in config_io_ctrl()
387 writel(ioregs->emif_sdram_config_ext, in config_io_ctrl()