2  * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4  * SPDX-License-Identifier:	GPL-2.0+
42 	writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);  in reset_cpu()
43 	writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);  in reset_cpu()
82 	{  7,  0x0,  500,  250,  250 },
83 	{  8,  0x0,  500,  250,  334 },
84 	{  9,  0x0,  500,  250,  500 },
100 	{ 25,  0x0, 1000,  500,  500 },
101 	{ 26,  0x0, 1000,  500,  667 },
102 	{ 27,  0x0, 1000,  333,  500 },
127 	{  0x4,  0x9, 1500, 750, 500 },
142 	val = readl(CONFIG_SAR2_REG);	/* SAR - Sample At Reset */  in get_sar_freq()
144 	val = readl(CONFIG_SAR_REG);	/* SAR - Sample At Reset */  in get_sar_freq()
178 	*sar_freq = sar_freq_tab[i - 1];  in get_sar_freq()
191 		puts("MV78230-");  in print_cpuinfo()
194 		puts("MV78260-");  in print_cpuinfo()
197 		puts("MV78460-");  in print_cpuinfo()
200 		puts("MV88F6720-");  in print_cpuinfo()
203 		puts("MV88F6810-");  in print_cpuinfo()
206 		puts("MV88F6820-");  in print_cpuinfo()
209 		puts("MV88F6828-");  in print_cpuinfo()
212 		puts("Unknown-");  in print_cpuinfo()
269  * main payload (U-Boot) is executed. This training code is currently
270  * only available in the Marvell U-Boot version. It needs to be
271  * ported to mainline U-Boot SPL at some point.
365  * This function is not called from the SPL U-Boot version
373 	 * Only with disabled MMU its possible to switch the base  in arch_cpu_init()
387 	 * in the macros / defines in the U-Boot header (soc.h).  in arch_cpu_init()
397 		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in arch_cpu_init()
404 	 * required for U-Boot. Calling update_sdram_window_sizes()  in arch_cpu_init()
509 	for (i = 0; i < dram->num_cs; i++) {  in ahci_mvebu_mbus_config()
510 		const struct mbus_dram_window *cs = dram->cs + i;  in ahci_mvebu_mbus_config()
512 		writel((cs->mbus_attr << 8) |  in ahci_mvebu_mbus_config()
513 		       (dram->mbus_dram_target_id << 4) | 1,  in ahci_mvebu_mbus_config()
515 		writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));  in ahci_mvebu_mbus_config()
516 		writel(((cs->size - 1) & 0xffff0000),  in ahci_mvebu_mbus_config()
547 	 * Armada 375 still has some problems with d-cache enabled in the  in enable_caches()
548 	 * ethernet driver (mvpp2). So lets keep the d-cache disabled  in enable_caches()
552 		/* Enable D-cache. I-cache is already enabled in start.S */  in enable_caches()
577 		setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_enable()
586 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_disable()