Lines Matching refs:CLK
35 #define CLK_LIST(CLK)\ argument
36 CLK(0, core_pll_clk)\
37 CLK(1, pass_pll_clk)\
38 CLK(2, tetris_pll_clk)\
39 CLK(3, ddr3a_pll_clk)\
40 CLK(4, ddr3b_pll_clk)\
41 CLK(5, sys_clk0_clk)\
42 CLK(6, sys_clk0_1_clk)\
43 CLK(7, sys_clk0_2_clk)\
44 CLK(8, sys_clk0_3_clk)\
45 CLK(9, sys_clk0_4_clk)\
46 CLK(10, sys_clk0_6_clk)\
47 CLK(11, sys_clk0_8_clk)\
48 CLK(12, sys_clk0_12_clk)\
49 CLK(13, sys_clk0_24_clk)\
50 CLK(14, sys_clk1_clk)\
51 CLK(15, sys_clk1_3_clk)\
52 CLK(16, sys_clk1_4_clk)\
53 CLK(17, sys_clk1_6_clk)\
54 CLK(18, sys_clk1_12_clk)\
55 CLK(19, sys_clk2_clk)\
56 CLK(20, sys_clk3_clk)\
57 CLK(21, uart_pll_clk)