Lines Matching refs:spd_cb
161 struct ddr3_spd_cb *spd_cb) in ddrtimingcalculation() argument
176 spd_cb->ddrspdclock = 2000000 / spd->t_ck; in ddrtimingcalculation()
177 clk_freq = spd_cb->ddrspdclock / 2; in ddrtimingcalculation()
194 spd_cb->ddrspdclock); in ddrtimingcalculation()
195 if (spd_cb->ddrspdclock == 1333) { in ddrtimingcalculation()
200 } else if (spd_cb->ddrspdclock == 1600) { in ddrtimingcalculation()
206 printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock); in ddrtimingcalculation()
297 spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024; in ddrtimingcalculation()
302 static void init_ddr3param(struct ddr3_spd_cb *spd_cb, in init_ddr3param() argument
305 spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; in init_ddr3param()
306 spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK); in init_ddr3param()
307 spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)); in init_ddr3param()
308 spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | in init_ddr3param()
310 spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) | in init_ddr3param()
312 spd_cb->phy_cfg.ptr2 = 0; in init_ddr3param()
313 spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) | in init_ddr3param()
315 spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) | in init_ddr3param()
318 spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK; in init_ddr3param()
319 spd_cb->phy_cfg.dcr_val = 1 << 10; in init_ddr3param()
322 spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK; in init_ddr3param()
323 spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29); in init_ddr3param()
326 spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | in init_ddr3param()
331 spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | in init_ddr3param()
336 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | in init_ddr3param()
339 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? in init_ddr3param()
343 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? in init_ddr3param()
347 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | in init_ddr3param()
351 spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | in init_ddr3param()
356 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | in init_ddr3param()
359 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; in init_ddr3param()
360 spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff); in init_ddr3param()
362 spd_cb->phy_cfg.zq0cr1 = 0x0000005D; in init_ddr3param()
363 spd_cb->phy_cfg.zq1cr1 = 0x0000005B; in init_ddr3param()
364 spd_cb->phy_cfg.zq2cr1 = 0x0000005B; in init_ddr3param()
366 spd_cb->phy_cfg.pir_v1 = 0x00000033; in init_ddr3param()
367 spd_cb->phy_cfg.pir_v2 = 0x0000FF81; in init_ddr3param()
370 spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 | in init_ddr3param()
376 spd_cb->emif_cfg.sdcfg |= 1 << 3; in init_ddr3param()
378 spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | in init_ddr3param()
384 spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 | in init_ddr3param()
387 spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 | in init_ddr3param()
392 spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 | in init_ddr3param()
398 spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff; in init_ddr3param()
401 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; in init_ddr3param()
439 int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb) in ddr3_get_dimm_params_from_spd() argument
449 if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) { in ddr3_get_dimm_params_from_spd()
454 strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18); in ddr3_get_dimm_params_from_spd()
455 spd_cb->dimm_name[18] = '\0'; in ddr3_get_dimm_params_from_spd()
457 init_ddr3param(spd_cb, &spd); in ddr3_get_dimm_params_from_spd()
459 dump_emif_config(&spd_cb->emif_cfg); in ddr3_get_dimm_params_from_spd()
460 dump_phy_config(&spd_cb->phy_cfg); in ddr3_get_dimm_params_from_spd()