305 	spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13;  in init_ddr3param()
306 	spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK);  in init_ddr3param()
307 	spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23));  in init_ddr3param()
308 	spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) |  in init_ddr3param()
310 	spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) |  in init_ddr3param()
312 	spd_cb->phy_cfg.ptr2 = 0;  in init_ddr3param()
313 	spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) |  in init_ddr3param()
315 	spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) |  in init_ddr3param()
318 	spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK;  in init_ddr3param()
319 	spd_cb->phy_cfg.dcr_val = 1 << 10;  in init_ddr3param()
322 		spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK;  in init_ddr3param()
323 		spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29);  in init_ddr3param()
326 	spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 |  in init_ddr3param()
331 	spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 |  in init_ddr3param()
336 	spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 |  in init_ddr3param()
339 	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ?  in init_ddr3param()
343 	spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ?  in init_ddr3param()
347 	spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 |  in init_ddr3param()
351 	spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 |  in init_ddr3param()
356 	spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 |  in init_ddr3param()
359 	spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;  in init_ddr3param()
360 	spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff);  in init_ddr3param()
362 	spd_cb->phy_cfg.zq0cr1 = 0x0000005D;  in init_ddr3param()
363 	spd_cb->phy_cfg.zq1cr1 = 0x0000005B;  in init_ddr3param()
364 	spd_cb->phy_cfg.zq2cr1 = 0x0000005B;  in init_ddr3param()
366 	spd_cb->phy_cfg.pir_v1 = 0x00000033;  in init_ddr3param()
367 	spd_cb->phy_cfg.pir_v2 = 0x0000FF81;  in init_ddr3param()
460 	dump_phy_config(&spd_cb->phy_cfg);  in ddr3_get_dimm_params_from_spd()