33 	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);  in ddr3_init_ddrphy()
38 	__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);  in ddr3_init_ddrphy()
40 	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);  in ddr3_init_ddrphy()
41 	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);  in ddr3_init_ddrphy()
42 	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);  in ddr3_init_ddrphy()
43 	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);  in ddr3_init_ddrphy()
48 	__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);  in ddr3_init_ddrphy()
50 	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);  in ddr3_init_ddrphy()
51 	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);  in ddr3_init_ddrphy()
52 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);  in ddr3_init_ddrphy()
53 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);  in ddr3_init_ddrphy()
54 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);  in ddr3_init_ddrphy()
55 	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);  in ddr3_init_ddrphy()
56 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);  in ddr3_init_ddrphy()
57 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);  in ddr3_init_ddrphy()
59 	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);  in ddr3_init_ddrphy()
60 	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);  in ddr3_init_ddrphy()
61 	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);  in ddr3_init_ddrphy()
63 	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()
97 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()
104 	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);  in ddr3_init_ddremif()
105 	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);  in ddr3_init_ddremif()
106 	__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);  in ddr3_init_ddremif()
107 	__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);  in ddr3_init_ddremif()
108 	__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);  in ddr3_init_ddremif()
109 	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);  in ddr3_init_ddremif()
110 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);  in ddr3_init_ddremif()
129 	__raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);  in ddr3_ecc_config()
135 		__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);  in ddr3_ecc_config()
138 		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |  in ddr3_ecc_config()
143 		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |  in ddr3_ecc_config()
247 	__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);  in ddr3_ecc_init_range()
281 	__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);  in cic_init()
284 	__raw_writel(0, base + KS2_CIC_CTRL);  in cic_init()
285 	__raw_writel(0, base + KS2_CIC_HOST_CTRL);  in cic_init()
288 	__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);  in cic_init()
297 	__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);  in cic_map_cic_to_gic()
300 	__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);  in cic_map_cic_to_gic()
374 	__raw_writel(tmp, KS2_DDR3APLLCTL1);  in ddr3_reset_ddrphy()
405 		__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);  in ddr3_err_reset_workaround()
406 		__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);  in ddr3_err_reset_workaround()
416 		__raw_writel(tmp_a, KS2_PSC_BASE +  in ddr3_err_reset_workaround()
426 		__raw_writel(tmp_b, KS2_PSC_BASE +  in ddr3_err_reset_workaround()
436 		__raw_writel(tmp, KS2_RSTCTRL);  in ddr3_err_reset_workaround()
444 		__raw_writel(tmp, KS2_RSTCTRL_RSCFG);  in ddr3_err_reset_workaround()